From e7a9a599107088e01d672b8d51d46cf1da097e29 Mon Sep 17 00:00:00 2001 From: Ettore Di Giacinto Date: Fri, 7 Aug 2026 02:10:37 +0000 Subject: [PATCH] =?UTF-8?q?feat(minimax-h3):=20encoder=20vision=20scatter?= =?UTF-8?q?=20(merged=E2=86=92prompt=5Fembeds=20+=20DeepStack=E2=86=92devi?= =?UTF-8?q?ce=20text=20tower)=20+=20ref2va=20re-attribution?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Closes the #86 framework residual and re-attributes the ref2va grid with a GB10 render A/B (row/H3-VISION-SCATTER). deepstack_visual_indexes CONFIRMED (was #86-inferred): {8,16,24}, grounded in the release config — MiniMax-H3's text_encoder/ IS Qwen3-VL-32B-Instruct, whose vision_config.deepstack_visual_indexes = [8,16,24], depth 27, text num_hidden_layers 64 (→50). Same as vllm-omni Qwen3VLMoeVisionConfig default and public Qwen/Qwen3-VL-30B-A3B. No value change; comment updated. Deliverable 1 — DEVICE scatter+inject WIRED 1:1 + GATED. MiniMaxH3EncoderTextForwardDevice now takes the optional visual_pos_mask + per-tap deepstack blocks and ADDS each block into the masked visual rows after each of the first len(deepstack) decoder layers — device mirror of the gated host reference and upstream _deepstack_process (encoder.py:770-800). The merged masked_scatter into inputs_embeds stays the caller's job (upstream _encode, encoder.py:1071). Text-only prompts pass the defaults and are byte-identical. Gate: the device keep-quant encoder test now also runs WITH a visual mask + two DeepStack blocks → device==host max|diff| 3.8e-4 (<=2e-3) AND DeepStack moves the conditioning (scale 1.006->1.062). Driver --cond-image routes a reference image through the encoder vision path (reuse only: Qwen3VLImageProcessor -> Qwen3VLVisionForward -> merged + 3 DeepStack; ExpandImagePlaceholders inserts nm image-pad tokens; masked_scatter; Qwen3VLGetRopeIndex == H3 _get_rope_index for t==1, position math verified). Additive. GB10 render A/B (256x256/22f/12steps): * Deliverable 3 — fl2va WITH the encoder vision path = COHERENT + matching (PASS): frame 0 the keyframe cat, frame 21 the cat on a WINDOWSILL in warm sunlight (evolved toward the prompt). No grid. The vision conditioning is SOUND. * Deliverable 2 — ref2va WITH the vision-enriched prompt STILL GRIDS (honest FAIL): same multicolour patch grid as #86's text-only ref2va. RE-ATTRIBUTION (evidence): the "vision-enriched conditioning fixes the grid" hypothesis is REFUTED. NOT the encoder conditioning — DiT math byte-exact (#74/#77), the SAME vision path renders a coherent fl2va, and the grid is invariant to text-only vs vision-enriched prompts. The only difference between coherent fl2va and gridding ref2va: fl2va PINS output rows (keyframe), ref2va PREPENDS free-running reference rows. Residual = the ref2va reference-row conditioning ASSEMBLY (MiniMaxH3EncodeReferenceImages VAE-reference rows + minimax_h3_packed_sequence_ref2va_blocks noised-anchor layout + un-pinned target-row denoise), NOT prompt_embeds and NOT the DiT forward. Records: spec §8.9 + §8.2 row, STATUS/BENCHMARKS/FEATURES H3 rows, benchmark-record, NOW, state. FOLLOWING_AGENTS_PROTOCOL Assisted-by: Claude Code:claude-opus-4-8 [ClaudeCode] --- .agents/NOW.md | 4 +- .agents/benchmark-record.md | 52 ++++++++ .agents/specs/minimax-h3.md | 67 ++++++++++- .agents/state.md | 45 +++++++ docs/BENCHMARKS.md | 4 +- docs/FEATURES.md | 4 +- docs/STATUS.md | 6 +- examples/minimax_h3_gen/main.cpp | 112 ++++++++++++++++-- .../vllm/model_executor/models/minimax_h3.h | 14 ++- .../models/minimax_h3_encoder_device.cpp | 31 ++++- .../models/minimax_h3_vision_gguf.cpp | 7 +- tests/vllm/models/test_minimax_h3.cpp | 31 +++++ 12 files changed, 351 insertions(+), 26 deletions(-) diff --git a/.agents/NOW.md b/.agents/NOW.md index 9c4b6421..b5ed4e4f 100644 --- a/.agents/NOW.md +++ b/.agents/NOW.md @@ -1,6 +1,6 @@ # NOW — the one-Read resume surface - + Read this FIRST, every session. A SNAPSHOT, rewritten in place: what is live, the gate being chased, what to do next. Never a log — evidence lives in the @@ -18,7 +18,7 @@ checkpoint on `upstream/main` at `59674cf1d`. | DeepSeek-V4-Flash decode | **Closed: beats ds4 1.144x** (`VT_V4_RESIDENT_W`, byte-exact); phase-2 residency NEG, default-OFF | — | | f32-out GEMV audit | Only laguna + ds4 bf16 tower affected; gate models unaffected | Re-verify ds4 tower same-tool | | Invocation-parity prevention | CI guard + AGENTS.md checklist landing | Merge; build-verify `kGemvHeuristicAlgos` on dgx | -| MiniMax-H3 lane | **vision tower RUNS on real weights + fl2va COHERENT** (`H3-CONDITIONED-E2E` PR#86: `visual.*` loader+probe; fl2va matched cat; ref2va grids) | scatter feats→embeds + DeepStack→text tower | +| MiniMax-H3 lane | **vision→cond scatter WIRED+gated; fl2va COHERENT via encoder path** (`H3-VISION-SCATTER` PR#90; indices {8,16,24} confirmed) | ref2va grids; residual = ref2va ref-row assembly (§8.9) | | Kimi-Linear-48B (KDA+NoPE-MLA+MoE) | **e2e RUNS** (bf16-resident §13): 13/13·656. Token gate **NEAR-TIE 106/128** | device GDN/MLA islands; 1.59 tok/s; default OFF | | 35B fresh grid | **BOUND** @`1ea26427`: 0.93-1.03x, c16 0.93x. INTAKE + Option A both NEGATIVE | Lever left: prefill glue (#61) | | Qwen3.5-4B revalidation | 0.9971x @`59674cf1` (#35); TTFT/PSS pass, TPOT/ITL open | `docs/bench-evidence/` | diff --git a/.agents/benchmark-record.md b/.agents/benchmark-record.md index 4a53c825..22a705f5 100644 --- a/.agents/benchmark-record.md +++ b/.agents/benchmark-record.md @@ -14310,3 +14310,55 @@ UNRELATED CUDA case (line 3503, "an NVFP4 checkpoint loads into a runnable DiT") isolation (585 assertions) and runs BEFORE the new case — a pre-existing cross-test CUDA resource-accumulation flake, not this change; the new loader gate passes standalone (59 assertions). + +## MiniMax-H3 ENCODER VISION SCATTER + ref2va re-attribution (`row/H3-VISION-SCATTER` PR #90, 2026-08-07, dgx sm_121a) + +Closes the #86 residual at the framework level and RE-ATTRIBUTES the ref2va grid with a GB10 +render A/B. Builds on #86 (real `visual.*` tower LOADS + fl2va COHERENT via VAE-keyframe). + +**`deepstack_visual_indexes` CONFIRMED (was #86-inferred).** `{8, 16, 24}` grounded in the +release config: MiniMax-H3's `text_encoder/` IS Qwen3-VL-32B-Instruct +(HF DeepBeepMeep/MiniMax-H3/Qwen3-VL-32B-Instruct/config.json), whose +`vision_config.deepstack_visual_indexes = [8, 16, 24]`, depth 27, text `num_hidden_layers = 64` +(→ min(64,50)=50). Identical to vllm-omni `Qwen3VLMoeVisionConfig` default and public +`Qwen/Qwen3-VL-30B-A3B-Instruct`. The #86 inference was right; no code value change. + +**Deliverable 1 — DEVICE scatter+inject WIRED 1:1 + GATED.** `MiniMaxH3EncoderTextForwardDevice` +now takes the optional `visual_pos_mask` + per-tap `deepstack` blocks and ADDS each block into the +masked visual rows after each of the first `len(deepstack)` decoder layers — device mirror of the +gated host reference and upstream `_deepstack_process` (encoder.py:770-800). The merged masked_scatter +into inputs_embeds stays the caller's job (upstream `_encode`, encoder.py:1071). Gate +(`test_minimax_h3 :: "the DEVICE keep-quant encoder matches the host f32 reference"`): device forward +now also runs WITH a visual mask + 2 DeepStack blocks → device==host max|diff| **3.8e-4** (≤ 2e-3) +AND DeepStack moves the conditioning (scale 1.006→1.062). PASS, 1562 assertions. Host text tower, +full vision tower, GGUF visual.* loader, MM processor all green. The full-suite SIGSEGV at line 3503 +(NVFP4 case) is the known cross-test CUDA flake — passes standalone (585 assertions), not this change. + +**Driver `--cond-image`** routes a reference image through the encoder vision path (reuse only: +Qwen3VLImageProcessor → Qwen3VLVisionForward → merged+3 DeepStack; ExpandImagePlaceholders inserts nm +image-pad tokens; masked_scatter; Qwen3VLGetRopeIndex == H3 `_get_rope_index` for t==1). Additive. + +**GB10 render A/B (256×256/22f/12steps).** +- **Deliverable 3 — fl2va WITH the encoder vision path = COHERENT + matching (PASS).** FL2VA GGUF + `--dequant-bf16` + `--first-frame` + `--cond-image` + `--partition fl2va`, prompt "a fluffy orange + cat sitting on a windowsill in warm sunlight". conditioning=[82,5120] (16 prompt + 66-token vision + block: 64 merged + 2 markers). Frame 0 = coherent orange cat (keyframe); frame 21 = the cat on a + WINDOWSILL in warm sunlight — the clip EVOLVED toward the prompt. No grid. Artifact + `~/h3fp4/out_vs_fl2va.mp4` (+ out_vs_fl2va/frame_*.ppm). The vision conditioning is SOUND. +- **Deliverable 2 — ref2va WITH the vision-enriched prompt STILL GRIDS (honest FAIL).** Ref2VA NVFP4 + `--fp4-resident` + `--ref-image` (VAE reference rows) + `--cond-image` + `--partition ref2va`, same + prompt. conditioning=[82,5120] (64 merged + 3 DeepStack), 1 reference image, latent 7×16×16. Every + frame (0/10/21) is the same multicolour PATCH GRID as #86's text-only ref2va. Artifact + `~/h3fp4/out_vs_ref2va.mp4`. + +**RE-ATTRIBUTION (with evidence).** The "vision-enriched conditioning fixes the grid" hypothesis is +REFUTED. The ref2va grid is NOT the encoder conditioning: (a) the DiT forward MATH is byte-exact vs +upstream (geometry ladder green every rung #74; device==host at real seq 1920 #77); (b) the SAME +vision scatter+DeepStack path renders a COHERENT fl2va-with-`--cond-image`; (c) the grid is INVARIANT +to text-only (#86) vs vision-enriched prompts. The only difference between coherent fl2va and gridding +ref2va: fl2va PINS output rows (keyframe cond rows) each step, ref2va PREPENDS free-running reference +rows. So the residual is the **ref2va reference-row conditioning ASSEMBLY** +(`MiniMaxH3EncodeReferenceImages` VAE-reference rows + `minimax_h3_packed_sequence_ref2va_blocks` +noised-anchor layout + how the denoise loop conditions the un-pinned target rows), NOT the prompt and +NOT the DiT forward. Next diagnostic: dump the ref2va target-row VAE-input adjacency-cosine (like #77's +0.95 for coherent fl2va) to confirm the target rows are white, and A/B the reference-row condition-noise. diff --git a/.agents/specs/minimax-h3.md b/.agents/specs/minimax-h3.md index 397c245b..ee734bb9 100644 --- a/.agents/specs/minimax-h3.md +++ b/.agents/specs/minimax-h3.md @@ -400,7 +400,7 @@ vLLM-Omni H3 modules at `vllm_omni/diffusion/models/minimax_h3/`; serving in | WebSocket `/v1/video/chat/stream`, `/v1/realtime/video` | `api_server.py:1593,1610` | — | **MISSING** (streaming/realtime) | | Request schema (prompt, size/w/h, num_frames, fps, seed, steps, refs) | `protocol/videos.py:97-249` | request contract (W7) | **PARTIAL** (core fields; frame-interp/lora/generate_sound absent) | | H3 knobs via `extra_params.{task,duration,flow_shift,audio_flow_shift}` | `pipeline:1034,403,1157-1158` | planner reads task/duration/shift | **DONE** | -| Modalities in: text/image/video/audio | `pipeline:1036-1104` | t2va (text) done; fl2va COHERENT on real weights (VAE-keyframe); vision tower now LOADS real `visual.*` + runs (probe); ref2va still grids | **PARTIAL** (vision-tower→DiT-conditioning scatter is the residual; §8.8) | +| Modalities in: text/image/video/audio | `pipeline:1036-1104` | t2va (text) done; vision tower LOADS real `visual.*` + runs; merged→prompt_embeds scatter + DeepStack→device text tower WIRED 1:1 + gated (§8.9); fl2va COHERENT via BOTH the VAE-keyframe AND the encoder vision path; ref2va still grids (residual RE-ATTRIBUTED to the ref2va reference-row assembly, NOT the conditioning) | **PARTIAL** (vision→conditioning scatter DONE §8.9; residual = ref2va reference-row assembly) | | Output: joint video+audio, 24 fps, 32 kHz stereo | `pipeline:106-111,1187` | frames + WAV + MP4 mux (W7) | **DONE** | | Scheduler: euler-ancestral rectified flow (single) | `scheduling_...euler_ancestral.py`; `time_request.py:34-61` | `MiniMaxH3EulerEta0Step` / `MiniMaxH3TimeShiftSigmas` | **DONE** | | CFG: distilled, no CFG (guidance params accepted+ignored; `cfg_parallel_size==1`) | `pipeline:250,275-276` | no CFG branch | **DONE** (matches) | @@ -709,3 +709,68 @@ extension; its e2e render verdict is recorded honestly in the benchmark record. DEVICE text tower) is the tracked residual that would let the vision-enriched-prompt hypothesis be tested. The `--ref-video` VAE encode is a slow single-thread CPU 3D-CNN path (separate perf limit). + +## 8.9 ENCODER VISION SCATTER — merged→prompt_embeds + DeepStack→device text tower (2026-08-07, `row/H3-VISION-SCATTER` PR #90) + +Closes the §8.8 residual at the FRAMEWORK level and RE-ATTRIBUTES the ref2va grid with a +render A/B. Three deliverables. + +**`deepstack_visual_indexes` CONFIRMED (was #86-inferred).** The value is `[8, 16, 24]`, +grounded in the release config: MiniMax-H3's `text_encoder/` IS **Qwen3-VL-32B-Instruct** +(HF `.../MiniMax-H3/.../Qwen3-VL-32B-Instruct/config.json`), whose +`vision_config.deepstack_visual_indexes = [8, 16, 24]`, depth 27, text `num_hidden_layers = 64` +(truncated to 50) — identical to vllm-omni's `Qwen3VLMoeVisionConfig` default and the public +`Qwen/Qwen3-VL-30B-A3B-Instruct` config. The #86 inference was correct; comment updated in +`minimax_h3_vision_gguf.cpp:46-52`. + +**Deliverable 1 — the DEVICE scatter+inject is WIRED 1:1 + GATED.** `MiniMaxH3EncoderTextForwardDevice` +(`minimax_h3_encoder_device.cpp:103,216-243`) now takes the optional `visual_pos_mask` + per-tap +`deepstack` blocks and, after each of the first `len(deepstack)` decoder layers, ADDS each block +into the masked visual-token rows — the device mirror of the gated host reference and of upstream +`MiniMaxH3Qwen3VLTextModel._deepstack_process` (`encoder.py:770-800`, +`hidden_states[visual_pos_masks] += visual_embeds`). The MERGED-feature masked_scatter into +`inputs_embeds` stays the caller's job (upstream `_encode` scatters it BEFORE the tower runs; +`encoder.py:1071`), exactly like the host reference. Text-only prompts pass the defaults and are +byte-identical. **Gate** (`test_minimax_h3.cpp :: "the DEVICE keep-quant encoder matches the host +f32 reference"`): the device forward now also runs WITH a visual mask + two DeepStack blocks and +checks device==host-reference (max|diff| **3.8e-4** ≤ 2e-3) AND that DeepStack MOVES the +conditioning (scale 1.006→1.062) — the surface #86 could not cover. All encoder/vision gates green +(host text tower + full vision tower + GGUF `visual.*` loader + MM processor). + +**Driver wiring — `--cond-image` routes a reference image through the ENCODER vision path** +(`examples/minimax_h3_gen/main.cpp`, mirroring `_encode`). Reuse-only: `Qwen3VLImageProcessor` → +`Qwen3VLVisionForward` (real `visual.*` tower) → merged `[nm,5120]` + 3 DeepStack blocks; +`ExpandImagePlaceholders` inserts `nm` image-pad tokens; merged masked_scatter into the embeds at +those rows; M-RoPE positions from `Qwen3VLGetRopeIndex` (byte-equivalent to H3's own +`_get_rope_index` for a single-frame image, t==1 — position math verified: text sequential, image +block the 3D grid, next-text advances by `max(llm_h,llm_w)`). Additive: without `--cond-image` the +text-only path is byte-identical. + +**GB10 RENDER A/B (2026-08-07, dgx sm_121a, 256×256/22f/12steps).** +- **Deliverable 3 — fl2va WITH the encoder vision path = COHERENT + matching (PASS).** FL2VA GGUF + (`--dequant-bf16`) + `--first-frame` (VAE-keyframe) + **`--cond-image`** (encoder vision) + + `--partition fl2va`, prompt "a fluffy orange cat sitting on a windowsill in warm sunlight". + Conditioning `[82,5120]` = 16 prompt + a 66-token vision block (64 merged image-pad rows + 2 + markers). Frame 0 = a coherent photorealistic ORANGE CAT matching the keyframe; frame 21 = the + same cat on a **WINDOWSILL in warm sunlight** — the clip EVOLVED toward the text prompt. No grid. + The vision-enriched conditioning is SOUND and load-bearing. Artifact `~/h3fp4/out_vs_fl2va.mp4`. +- **Deliverable 2 — ref2va WITH the vision-enriched prompt STILL GRIDS (honest FAIL).** Ref2VA NVFP4 + (`--fp4-resident`) + `--ref-image` (VAE reference rows) + **`--cond-image`** (encoder vision) + + `--partition ref2va`, same prompt. Conditioning `[82,5120]` (64 merged + 3 DeepStack), 1 reference + image, latent 7×16×16. Every frame (0/10/21) is the same multicolour PATCH GRID as #86's + text-only ref2va. Artifact `~/h3fp4/out_vs_ref2va.mp4`. + +**RE-ATTRIBUTION (with evidence).** The mission's "vision-enriched conditioning fixes the grid" +hypothesis is **REFUTED**. The ref2va grid is NOT the encoder conditioning: (a) the DiT forward MATH +is byte-exact vs upstream (§8.5 geometry ladder green every rung; §8.6 device==host at real seq +1920); (b) the vision scatter+DeepStack is proven sound by the COHERENT fl2va-with-`--cond-image` +render — the SAME conditioning path; (c) the ref2va grid is INVARIANT to text-only (#86) vs +vision-enriched (this row) prompts. The ONLY thing that differs between the coherent fl2va and the +gridding ref2va is that **fl2va PINS output rows (keyframe cond rows) each denoise step** while +**ref2va PREPENDS free-running reference rows** — so the residual is the **ref2va-specific +reference-row conditioning ASSEMBLY** (`MiniMaxH3EncodeReferenceImages` VAE-reference rows + +`minimax_h3_packed_sequence_ref2va_blocks` noised-anchor layout + how the denoise loop conditions +the un-pinned target rows on them), NOT the prompt_embeds and NOT the DiT forward. Next diagnostic: +dump the ref2va target-row VAE-input latent adjacency-cosine (like #77 did for the coherent fl2va, +0.95) to confirm the target rows are white, and A/B the reference-row condition-noise vs a clean +anchor. diff --git a/.agents/state.md b/.agents/state.md index 7786b03a..e8d5f80c 100644 --- a/.agents/state.md +++ b/.agents/state.md @@ -40259,3 +40259,48 @@ kept). Records: spec §8.8 + §8.2, STATUS/BENCHMARKS/FEATURES, benchmark-record Note also that `agent-record` was ALREADY failing on `main` at `4cfeee13` before this merge (`check-fusion-consistency`, `minimax_h3_video_vae_device`), verified on `origin/main` itself. That one is not from this work. + +## 2026-08-07T04:10 - MiniMax-H3 ENCODER VISION SCATTER wired+gated; fl2va COHERENT via encoder vision path; ref2va grid RE-ATTRIBUTED to the reference-row assembly (row/H3-VISION-SCATTER, helper, PR #90) + + +Closes the #86 framework residual and re-attributes the ref2va grid with a GB10 render A/B. + +**deepstack_visual_indexes CONFIRMED (was #86-inferred).** `{8,16,24}` grounded in the release +config: H3's text_encoder/ IS Qwen3-VL-32B-Instruct, whose vision_config.deepstack_visual_indexes = +[8,16,24], depth 27, text num_hidden_layers 64 (→50). Same as vllm-omni Qwen3VLMoeVisionConfig +default and public Qwen/Qwen3-VL-30B-A3B. No value change; comment updated (minimax_h3_vision_gguf.cpp). + +**Deliverable 1 — DEVICE scatter+inject WIRED 1:1 + GATED.** MiniMaxH3EncoderTextForwardDevice +(minimax_h3_encoder_device.cpp:103,216-243) now takes visual_pos_mask + per-tap deepstack blocks and +ADDS each block into the masked visual rows after each of the first N decoder layers — device mirror of +the gated host reference and upstream _deepstack_process (encoder.py:770-800). Merged masked_scatter +into inputs_embeds stays the caller's job (upstream _encode). Text-only byte-identical (defaults). +Gate: device keep-quant encoder test now runs WITH a visual mask + 2 DeepStack blocks → device==host +max|diff| 3.8e-4 (≤2e-3), DeepStack moves conditioning (scale 1.006→1.062); PASS 1562 assertions. +Host text tower + full vision tower + GGUF visual.* loader + MM processor all green. NVFP4 line-3503 +SIGSEGV is the known standalone-passing cross-test flake, not mine. + +**Driver --cond-image** routes an image through the encoder vision path (reuse: Qwen3VLImageProcessor → +Qwen3VLVisionForward → merged+3 deepstack; ExpandImagePlaceholders; masked_scatter; Qwen3VLGetRopeIndex +== H3 _get_rope_index for t==1, position math verified). Additive. + +**GB10 render A/B (256x256/22f/12steps).** +- fl2va + --cond-image = COHERENT + matching (deliverable 3 PASS): FL2VA GGUF --dequant-bf16 + + --first-frame + --cond-image + --partition fl2va, conditioning [82,5120] (64 merged + 3 deepstack). + Frame 0 = coherent orange cat (keyframe); frame 21 = cat on a WINDOWSILL in warm sunlight (evolved + toward the prompt). No grid. Artifact ~/h3fp4/out_vs_fl2va.mp4. Vision conditioning is SOUND. +- ref2va + --cond-image STILL GRIDS (deliverable 2, honest FAIL): Ref2VA NVFP4 --fp4-resident + + --ref-image + --cond-image + --partition ref2va, conditioning [82,5120], latent 7x16x16. Every frame + the same multicolour patch grid as #86. Artifact ~/h3fp4/out_vs_ref2va.mp4. + +**RE-ATTRIBUTION (evidence).** The "vision-enriched conditioning fixes the grid" hypothesis is REFUTED. +NOT the encoder conditioning: (a) DiT forward math byte-exact (geometry ladder #74, device==host seq +1920 #77); (b) SAME vision scatter path renders a COHERENT fl2va; (c) grid invariant to text-only vs +vision-enriched prompt. Only difference: fl2va PINS output rows (keyframe), ref2va PREPENDS free-running +reference rows. Residual = the ref2va reference-row conditioning ASSEMBLY (MiniMaxH3EncodeReferenceImages +VAE-reference rows + minimax_h3_packed_sequence_ref2va_blocks noised-anchor layout + un-pinned target-row +denoise), NOT prompt_embeds and NOT the DiT forward. Next: dump ref2va target-row VAE-input adjacency +cosine (vs #77's 0.95 for coherent fl2va) + A/B the reference-row condition-noise. + +Box left clean (renders exited, GPU idle, gpu.lock released, worker stays parked, temp PNGs pruned, +ckpts kept). Records: spec §8.9 + §8.2 row, STATUS/BENCHMARKS/FEATURES H3 rows, benchmark-record, NOW. diff --git a/docs/BENCHMARKS.md b/docs/BENCHMARKS.md index 5d0ab2ad..d09ba967 100644 --- a/docs/BENCHMARKS.md +++ b/docs/BENCHMARKS.md @@ -311,13 +311,13 @@ built on it rather than keeping the flattering one. | vLLM 0.26 re-benchmark | Pending | Re-run the binding grids on the advanced pin | | MiniMax-H3 FP4 speed (W-FP4a) | **Measured GB10 (`row/H3-FP4-GPU-E2E`).** Marlin W4A16 byte-exact vs bf16; fp4 a memory win, 0.8x bf16/forward. Real-ckpt fp4-resident e2e RUNS (mp4/wav) | fp4 speed CLOSED. Detail: benchmark-record + spec §8 | | MiniMax-H3 render coherence (`row/H3-RENDER-CLOSE` #77) | **CLOSED: a COHERENT scene on GB10.** #70/#74 white was wrong-PARTITION usage (t2va on the ref2va ckpt); t2va on the FL2VA GGUF renders a prompt-matched orange cat (adj-cos 0.95 vs 0.06, no patch-grid) | Verified first: t2va inputs byte-exact vs upstream; CUDA device==host at seq 1920. Follow-up `H3-TASK-PARTITION-GUARD`: the task/partition mismatch now RAISES 1:1 with `_resolve_task` (spec §8.6-8.7) | -| MiniMax-H3 image conditioning (`row/H3-CONDITIONED-E2E`) | **Vision tower RUNS on REAL weights (GB10) + fl2va COHERENT.** GGUF `visual.*`→`Qwen3VLVisionWeights` loader + Qwen3VLProcessor reuse; tower forward finite. fl2va (VAE-keyframe) renders a matched cat; ref2va STILL grids | ref2va needs the vision→DiT-conditioning scatter (residual); frame-sanity + probe in benchmark record + spec §8.8 | +| MiniMax-H3 image conditioning (`row/H3-CONDITIONED-E2E`, `row/H3-VISION-SCATTER`) | **Vision→cond scatter WIRED+gated; fl2va COHERENT via encoder path.** merged→prompt_embeds + DeepStack→device text tower (device==host 3.8e-4); fl2va+`--cond-image` matched cat → prompt scene; ref2va STILL grids | grid RE-ATTRIBUTED to the ref2va reference-row assembly, NOT the conditioning (DiT math byte-exact; vision sound per the coherent fl2va A/B); indices {8,16,24} confirmed. §8.9 | | MXFP4 Qwen3-8B (W4A16 Marlin) | **`KERNEL-MARLIN-DENSE-EXEC` x3 (dense-ON default): c1 1.020, c2/c4/c8 0.962/0.966/0.969, GPU mem 2.63x less** (beats #51 1.005/0.925/0.939/0.953 EVERY axis); #44 3/3, 32B-NVFP4A16 6/6; -Werror test-guard fixes x2 | **VT_MARLIN_DENSE default-ON** (+951us). `FLASH-PTXAS` #82: cuModule A/B ties our+vLLM PTX across ptxas 13.0/13.2/driver-JIT (~144us); +10us is engine CONTEXT not codegen, no ptxas lever/flip (retires #75) | | Vulkan vs llama.cpp Vulkan (`BENCH-VK-LLAMA`) | **NOT APPLICABLE: no number measured, claimed or owed.** Vulkan registers 8 of the CPU backend's 83 ops and runs no model. The 2026-08-06 campaign spec is PLAN ONLY. [Detail](../.agents/specs/vulkan-full-support.md) | `VK-E`: build llama.cpp `-DGGML_VULKAN=ON` at pin `237ad9b96` on dgx, `llama-bench` on the same GGUF, record three columns (ours-Vulkan, llama.cpp-Vulkan, ours-CUDA). Blocked by `VK-B` and by `glslc` on the gate box | | Memory footprint vs declared workload (`ROAD-V1-MEM`, #83) | **Never measured, and not measurable today**: there is no auto-sizing to compare against, because the KV pool is a hand-typed `--num-blocks`, so "what the run actually needed" has no number | Once M1's `MemoryBudget` lands: predicted-vs-actual bytes per allocation class, then peak footprint ours-auto vs vLLM at its 0.9 default on the same model and config | | Startup latency (cold launch to first `/health`) | **PENDING: no number measured or claimed.** Listed in the gate protocol, never captured (readiness polled every 5 s, duration discarded). Harness landed 2026-08-06. [Detail](../.agents/specs/startup-latency-axis.md) | Run `dgx-online-serving.sh --startup-only --model 27` on dgx (needs a CUDA `server` build; the box was at 100% disk on 2026-08-06), then record ours/vLLM medians and the ratio here | | Speculation depth (`ROAD-V1-D3-SPEC-K`, #81) | **Never measured, MTP is k=1** (our port covers vLLM's k=1 branch only), so no acceptance-vs-depth curve exists | k=2..4 three-way greedy gate, then the c1/c>1 A/B + the per-workload (prose vs code) acceptance-vs-depth curve any dynamic or adaptive depth policy needs | -| Vulkan vs llama.cpp Vulkan (`BENCH-VK-LLAMA`) | **NOT APPLICABLE: nothing measured, claimed or owed.** 16 NATIVE kernels; 71 on the host tier. opt-125m runs e2e token-exact on llvmpipe; no speed measured. [Detail](../.agents/specs/vulkan-full-support.md) | `VK-E`: llama.cpp `-DGGML_VULKAN=ON` at `237ad9b96` on dgx, `llama-bench`, same GGUF, three columns (ours-Vulkan, llama.cpp-Vulkan, ours-CUDA). Until then: `GetReferenceTierHits()` must reach 0 | +| Vulkan vs llama.cpp Vulkan (`BENCH-VK-LLAMA`) | **NOT APPLICABLE: nothing measured, claimed or owed.** 16 NATIVE kernels; 71 on the host reference tier. opt-125m runs e2e token-exact; no speed measured. [Detail](../.agents/specs/vulkan-full-support.md) | `VK-E`: llama.cpp `-DGGML_VULKAN=ON` at `237ad9b96` on dgx, `llama-bench`, same GGUF, three columns (ours-Vulkan, llama.cpp-Vulkan, ours-CUDA). Until then: `GetReferenceTierHits()` must reach 0 | | SGLang floor arms | Never ran | Both arms of the SGLang comparison | | cuBLAS invocation-parity guard | CI guard landed (CPU); `kGemvHeuristicAlgos` refactor build-verify owed | `nvcc` rebuild + SACRED gate on dgx | | Ampere consumer (`sm_86`, RTX 3090 class) | **No number owed; no such board here.** 2026-08-06 build-verify: 7/7 FA2 TUs 0-warn, real `sm_86` SASS. [Detail](../.agents/benchmark-record.md) | External RTX 3090 report. Floor is llama.cpp on that card (GGUF, not our Blackwell-only NVFP4 grid) | diff --git a/docs/FEATURES.md b/docs/FEATURES.md index 8f8cddc2..a29a3765 100644 --- a/docs/FEATURES.md +++ b/docs/FEATURES.md @@ -133,7 +133,7 @@ they sit outside the gated list above. |---|---|---|---| | Voxtral audio (`VoxtralForConditionalGeneration`) | Voxtral-Mini-3B-2507 | near-tie-robust 16/16 vs vLLM 0.25.0 | decode 0.97x (beats vLLM); encoder TTFT ~17x, pending | | Whisper audio encoder | openai/whisper-small; whisper-large-v3 (Voxtral cfg) | encoder tower 77/77; large-v3 tower 203/203 | pending | -| MiniMax-H3 DiT (`MiniMaxH3DiTModel`, vllm-omni lane) | MiniMax-H3 (33.1B video+audio) | portable path 66/66 (DiT geometry ladder + CUDA-vs-host at seq 1920); t2va + fl2va render COHERENT prompt/frame-matched scenes on GB10; encoder vision tower now RUNS on real `visual.*` weights (probe); ref2va still grids | FP4/Marlin landed; ref2va conditioning + speed pending | +| MiniMax-H3 DiT (`MiniMaxH3DiTModel`, vllm-omni lane) | MiniMax-H3 (33.1B video+audio) | portable 66/66 (ladder + CUDA-vs-host seq 1920); t2va+fl2va COHERENT on GB10 (fl2va via VAE-keyframe + encoder path); merged→prompt_embeds + DeepStack→text tower wired+gated; ref2va grids (residual = ref2va ref rows) | FP4/Marlin landed; ref2va reference-row conditioning + speed pending | | MTP speculator | Qwen3.6-27B, Qwen3.6-35B-A3B | token-identical to vLLM `mtp` at c1 | ~4% faster c1; +16% output tput (MoE) | | DFlash block-diffusion | Qwen3 (DFlash draft) | near-tie e2e 27/27 vs vLLM | 2.9x over spec-off, 1.003x vs vLLM DFlash-on | | DeepSeek-V4 MTP | DeepSeek-V4-Flash (nextn head) | lossless 5/5; real-model weight-blocked | pending | @@ -161,7 +161,7 @@ model architecture is wired. | Image | ✅ correctness-gated | ✅ | ✅ | ◐ | | Video | ✅ correctness-gated | ✅ | ✅ | ☐ | | Audio | ✅ correctness-gated | ✅ | ◐ | ◐ | -| Video+audio GENERATION (MiniMax-H3 DiT, vLLM-Omni lane) | ◐ t2va + fl2va render COHERENT scenes on GB10 (fl2va first-frame VAE-keyframe); guard mirrors `_resolve_task`; vision tower RUNS on real weights (probe, §8.8); ref2va still grids | ✅ (vllm-omni, BF16-only, no quantized H3 arm) | ☐ | ☐ | +| Video+audio GENERATION (MiniMax-H3 DiT, vLLM-Omni lane) | ◐ t2va+fl2va COHERENT on GB10 (fl2va via VAE-keyframe AND encoder vision path); merged→prompt_embeds + DeepStack→text tower wired+gated (§8.9); guard mirrors `_resolve_task`; ref2va grids (residual = ref2va ref rows) | ✅ (vllm-omni, BF16-only, no quantized H3 arm) | ☐ | ☐ | | Multimodal over the OpenAI server | ☐ | ✅ | ✅ | ◐ | Image, video and audio are correct through the CLI and library. Serving them diff --git a/docs/STATUS.md b/docs/STATUS.md index 74960f65..c625b354 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -85,7 +85,7 @@ token-for-token correctness against the pinned oracle. | OLMo-3 dense (dual rope, interleaved sliding window) | Implemented, oracle-blocked | Loads + runs in our engine (dual rope: plain sliding + YaRN full-attn, per-layer sliding window); no SACRED gate: vLLM 0.25.0 oracle cannot run OLMo-3-1025-7B (`KeyError: 'rope_theta'`; transformers 5.13.1 nests `rope_parameters` per layer-type, no flat `rope_theta`; run-verified W0 2026-07-26) | | Laguna-S-2.1 MoE (`LagunaForCausalLM`, 118B/8B) | **BINDING 2026-08-04: 87% of vLLM (37.55 vs 43.10, SAME-TOOL nsys both engines); the whole +3.1 ms/step is the bf16 M=1 GEMV bucket (2/3 o_proj, ~196-204 vs 139 us/call, identical `gemvx` kernel); attention/MoE/glue tied or ours-ahead. Invocation match (bf16-out `cublasGemmEx`) A/B'd = WASH, ruled out; ROOT CAUSE FOUND 2026-08-04 (`VT_LAGUNA_RESIDENT_BF16W`): the bf16 projections read UNIFIED/ATS host memory, not `cudaMalloc`'d device memory — staging them device-resident (byte-exact ids) gives 38.8→44.6 tok/s (o_proj 194→131, lm_head 2410→1620 us/call), parity+ vs vLLM 43.1; **default-ON** (flip smoke-verified: canonical byte-exact ids, 44.6 clean-median). Earlier ceiling/diffuse verdicts below were cross-tool artifacts.** **REAL vLLM BAR ESTABLISHED (2026-07-31, `CLAIM-LAGUNA-VLLM-NVFP4`): FIRST-EVER vLLM Laguna run** — prior numbers (incl. the correctness oracle) were all llama.cpp, never vLLM. vLLM on official `poolside/Laguna-S-2.1-NVFP4` (single GB10, greedy, eager, MARLIN backend forced via `VLLM_TEST_FORCE_FP8_MARLIN=1` because the auto-default `FLASHINFER_CUTLASS` needs an absent `nvcc`): **~18.8 tok/s** (64-tok steady) — a LOWER bound. Our GGUF-Q4_K engine = 7.7 tok/s (vLLM ~2.4×); llama.cpp GGUF = 27.8 (still fastest at batch-1). llama.cpp is now a labeled SECONDARY "beat best-in-class GGUF" note; vLLM-NVFP4 is the headline bar. TRUE apples-to-apple still owes OUR NVFP4 Laguna forward arm (same tensor-core path as 27B/35B) — bring-up W-plan SPEC'D in `.agents/specs/laguna-nvfp4-arm-2026-07-31.md` (~85% reuse of the 35B NVFP4 W4A4 MoE infra + a name-map; bf16 attn/dense + fp4 experts; N1-N5 bricks, DGX-gated). **N1-scaffold LANDED (2026-07-31):** additive `LagunaMoeWeights.experts_{gate,up,down}_fp4` + `shared_{gate,up,down}_fp4` (`Nvfp4Weight`, mirror qwen3_5), dead until the N1 loader; CPU build clean + `test_laguna_scaffold` 8/8·167 unchanged. **N1b loader IMPLEMENTED (2026-07-31, build-verified):** `LoadLagunaForCausalLMWeights` (`laguna_weights.cpp`) replaces the `VT_CHECK(false)` stub — resolver + per-layer `LoadBf16Direct` (attn/dense/norms/embed/lm_head/router/shared-expert) + F32 `e_score_correction_bias` + `LnLoadCtNvfp4Raw` W4A4 experts. Name-map + dtypes VERIFIED against the real `poolside/Laguna-S-2.1-NVFP4` index (router `mlp.gate` BF16, bias F32, experts W4A4, shared-expert BF16). **N1b RUN-VERIFIED (2026-07-31):** loader round-trips a synthetic NVFP4 checkpoint byte-identically (`test_laguna_nvfp4_loader` 2/2·29; full detail in the benchmark record). **N2 FORWARD-BRANCH LANDED + CPU-GATED (2026-07-31):** `LqGemmNvfp4Fp4` (per-expert TRUE-W4A4: `ScaledFp4Quant(input_global_scale_inv)`→`MatmulNvfp4Fp4(alpha)`, unified-memory pattern like `LqGemm`) + `LagunaFfnBlock` branches on `fp4=!experts_gate_fp4.empty()` (routed experts fp4; keep-quant grouped fast-path gated off `!fp4`; bf16 attn/dense/router/shared-expert/lm_head unchanged) + both `LagunaForwardGguf{,Cached}` guards relaxed to `has_gguf_weights||has_nvfp4_weights`. **CORRECTION:** routed experts are W4A4 ⇒ per-expert `MatmulNvfp4Fp4`, NOT the grouped W4A16 `MoeGroupedGemmNvfp4` (grouped W4A4 deferred to N5 speed). `test_laguna_nvfp4_loader` 3/3·61 (added a forward run-gate: fp4 MoE branch runs through the real `LagunaForwardGguf` → finite+deterministic logits + routed-experts-consumed); `test_laguna_scaffold` 8/8 unchanged (GGUF byte-identical). **N3 DRIVER LANDED + CPU-SMOKE-VERIFIED (2026-07-31):** `examples/laguna_gen` auto-detects a safetensors DIRECTORY (→ NVFP4: `LoadHfConfig(config.json)` + `LoadLagunaForCausalLMWeights` + `LagunaForwardGguf{,Cached}`) vs a `.gguf` FILE (→ keep-quant), sharing the greedy loop; `--token-ids` bypass the tokenizer for the id-vs-golden gate. Verified on a synthetic NVFP4 dir with a REAL config.json (exercises the `LoadHfConfig`→`ParseLagunaParams` seam the loader test bypassed) → `has_nvfp4=1`, KV-cache decode runs finite. **N4 RAN on GB10 (2026-08-01) — the arm works end-to-end; correctness coherent+near-tie, speed 120× off.** git-archived `84fab587` → clean CUDA build (`121a`) → `laguna-gen --gpu` on the real 67 GiB `ckpt` with vLLM's exact prompt ids injected (`2,785,9626,377,15360,395`, captured via the HF tokenizer). Two GB10 memory fixes landed to run: release the mmap'd shards after the loader's memcpy-copy (114→67 GiB RSS), and create the CUDA context BEFORE the load (the 67 GiB reclaimable page cache otherwise starves `cudaStreamCreate`). **Correctness:** ours `22345 83 350 71070 395 340 9626 372 1703 …` vs golden `22345 83 290 350 674 330 5541 966 340 9626 377 15360 …` — **first 2 tokens match vLLM exactly**, then near-tie divergence; coherent ("France is" = 9626/377/15360; shares golden vocab). EXPECTED: our TRUE-W4A4 (fp4 activations) vs the MARLIN golden's W4A16 (bf16 activations) — different precision, not a bug. **Speed: 6.34 s/tok (0.16 tok/s), prefill 17.3s — ~120× slower than vLLM 18.8.** ROOT CAUSE (source-confirmed): `LqGemmNvfp4Fp4` uses the generic `vt::MatmulNvfp4Fp4` = the hand-written EMULATION CUDA kernel, NOT the cutlass sm120a fp4 tensor-core path the 27B/35B W4A4 use (`MatmulNvfp4Fp4DirectD`); + per-expert loop + per-GEMM host sync + no device residency. **nsys (2026-08-01) trace-confirmed + refined:** only 2 GPU kernels — `MatmulNvfp4Fp4Naive` = 99.3% of GPU time + fp4-quant 0.7%; GPU busy only ~18% of wall. NO bf16 GEMM on the GPU ⇒ `LqGemm`'s bf16 branch runs the host `MatmulNK` reference on the CUDA queue (attention/dense/router/shared/lm_head are CPU-bound, ~4.8 s/tok) — a second lever the source scan missed. **N5 LEVER #2 LANDED (2026-08-01) — 16× decode.** Routed the bf16 tower (attention/dense/router/shared/lm_head) off the host `MatmulNK` onto the GPU (`LqGemm` bf16 branch: `vt::CastBf16` the small activation + `vt::MatmulBT` bf16×bf16→f32, weight stays bf16 — no per-token `ReadF32` of `lm_head [100352,H]`): **decode 6.34 → 0.39 s/tok (16.3×; 0.16 → 2.56 tok/s), prefill 17.3 → 2.24s**; coherence preserved (near-tie). CPU path unchanged (run-gate byte-identical). **N5 LEVER #1 LANDED (2026-08-01) — native fp4 tensor-core, another ~2×.** The engine's native sm120a fp4 tensor-core MMA (`MatmulNvfp4Fp4Native`, `mma.sync kind::mxf4nvf4`) reads the same linear scale layout `LqGemmNvfp4Fp4` produces — it was gated OFF behind `VT_NVFP4_FP4_NATIVE`; the Laguna driver now defaults it ON (scoped; 27B/35B untouched). **decode 0.39 → ~0.20-0.24 s/tok (~2×; ~4.2-5.0 tok/s)**; coherent (byte-identical ids to the emulation path — numerically equivalent), first token matches the golden. **Cumulative N5: 0.16 → ~4.5 tok/s (~28×), now ~4× from vLLM 18.8.** **Device-resident MoE block LANDED + MEASURED (2026-08-01, `LagunaMoeResidentFp4`, `VT_LAGUNA_RESIDENT_MOE` default-ON):** the whole token's routed experts as ONE async device chain (fp4-quant→GEMM gate/up, `MoeSiluMul`, →down stacked, ONE `MoeCombine`), draining once vs ~Pk×3 syncs. **Speed EAGER-NEUTRAL (0.20 s/tok)** — empirically confirms the ds4 precedent (per-op syncs overlap GPU compute; wall is GPU-serial-bound; the graph is the payoff). **CORRECTNESS WIN: golden-token match 2 → 13** (the device `MoeSiluMul`/`MoeCombine` mirror vLLM's fused MoE faithfully). Lands default-ON (better correctness, no speed cost, graph prerequisite). **CORRECTED CEILING (from the measured state): a perfect decode graph caps at ~5.9 tok/s** (GPU already ~87% busy at 0.20 s/tok), still 3.3× short of vLLM 18.8 — the graph is necessary but NOT sufficient; the remaining 3.3× is KERNEL EFFICIENCY (native fp4 MMA ~302µs/M=1 expert GEMM vs vLLM's tuned cutlass sm120a fp4 + fused norm/quant/silu). Parity = TWO campaigns: (A) device-resident+graph → ~5.9; (B) cutlass DirectD experts + fused ops + M=1-tuned GEMV → the rest. **CAMPAIGN-B FIRST BRICK LANDED (2026-08-01): coalesced M=1 fp4 GEMV** (`MatmulNvfp4Fp4Gemv`, one warp/column, coalesced weight-row reads, `VT_NVFP4_FP4_GEMV` default-ON) — same-binary A/B: **decode 0.20 → 0.15 s/tok (1.33×; → ~6.7 tok/s), prefill 1.14 → 0.86s**, coherent+near-tie. **Cumulative this session: 0.16 → ~6.7 tok/s (~42×), now ~2.8× from vLLM 18.8.** (ILP variant `kCpw=4` measured SLOWER — 0.21 s/tok, occupancy loss > activation-reuse gain — reverted to `kCpw=1`; kernel kept templated as a re-measurable knob.) **ncu of the GEMV (sudo): sm__throughput 35-71%, DRAM n/a — COMPUTE/LATENCY-bound, not BW-bound.** Corrects the earlier "~6× BW → ~16-17 tok/s" estimate: the next GEMV lever is HARDWARE fp4 dequant (`cvt.e2m1x2`), not more bandwidth. Parity (18.8) is a multi-brick campaign (decode graph + fused norm/quant + hardware-dequant GEMV), not one more kernel. **B0 hw-fp8 SCALE-decode: MEASURED NEGATIVE, reverted (2026-08-01, `ab7a1c1e`).** Replacing the GEMV's per-byte software fp8-e4m3 group-scale decode (`F8E4M3ToF32Dev`/`ldexpf`) with hardware `cvt.rn.f16.e4m3` (`__nv_fp8_e4m3`→float) is bit-exact (ids byte-identical on the real ckpt) but paging-immune ncu shows it NEUTRAL-to-slightly-WORSE (grid768 41.2 vs 41.9µs tie; mean 53.6 vs 49.4µs) — GPU `ldexpf` is a cheap exponent-bit add, not a libcall. NOTE this is the fp8 SCALE decode, NOT the fp4-e2m1 WEIGHT dequant (the `kE2M1` `__constant__` LUT); the LUT→arithmetic/`cvt.e2m1x2` weight-dequant is a SEPARATE still-open lever (spec brick B1). Also: end-to-end wall-clock is unusable for kernel A/B here (67 GiB unified reload swings TPOT 0.16↔1.08 s/tok run-to-run) — kernel-duration ncu is the only honest anchor. **★ B2 SCOPED + DE-RISKED (2026-08-01, zero-DGX) — the real 18.8 lever:** vLLM's 18.8 bar is MARLIN W4A16 (`VLLM_TEST_FORCE_FP8_MARLIN=1`), which is LOW-M-optimized (decode-correct, unlike a tensor-core W4A4 GEMM that wastes M=1 tile rows). The engine already ships the EXACT kernel `vt::MoeGroupedGemmNvfp4Marlin` (1:1 lift of vLLM `moe_wna16_marlin_gemm`) + shared `MarlinRepackExpertWeight`, and qwen3_5 (27B/35B) already routes its NVFP4 experts through it (default-ON `VT_NVFP4_MARLIN`, 16/16-vs-oracle, +22% gate/+80% decode) via `BuildMoeMarlinResident`. So B2 = mirror that for `LagunaMoeWeights.experts_*_fp4` (a `BuildLagunaMoeMarlinResident` reusing the shared repack + route `LagunaFfnBlock`'s fp4 branch to the Marlin grouped GEMM, GEMV kept as the `=0` escape hatch) — pure reuse, no new kernel, matches vLLM's exact W4A16 numerics. **B2 IMPLEMENTED (2026-08-01, `3c49ef37`) — COMPILES CLEAN on GB10 sm_121a, runtime bug pending.** `LagunaMoeResidentMarlin` + `BuildLagunaMoeMarlinResident` (laguna.cpp, `#ifdef VT_MARLIN_NVFP4`) reconstruct the MoE Marlin path over the SHARED `dense_nvfp4::Dev`/`DBuf`/`ResidentNvfp4` + shared `vt::cuda` Marlin repack/align ops + `vt::MoeGroupedGemmNvfp4Marlin`; SACRED 27B/35B path BYTE-UNTOUCHED; gated `VT_LAGUNA_MARLIN_MOE=1` **default-OFF** (zero regression to the default GEMV path). Compiles clean on the full CUDA build. RUN: loads OK (48 layers, 256 experts) but the FIRST FORWARD device-faults silently on the Marlin path — a layout/param bug (suspects: `MoeCombine` bf16-in/f32-out dtype, the down-GEMM reusing the gate/up align, or the fp4-original free omitted → mem ~doubles). NEXT: `compute-sanitizer` localize → fix → near-tie vs the vLLM-Marlin golden + kernel-duration ncu → flip default-ON. Default path unaffected. **UPDATE (`22d6e146`): added the qwen3_5-style fp4-original free after repack** (device transients + host bytes; peak was ~3× the expert tower → past the 119 GiB pool → null-alloc → silent fault the likely cause); compiles clean. The runtime gate stayed INCONCLUSIVE this session (contended/orphaned processes on the shared box, no captured ids) — rerun on a clean uncontended session, compute-sanitizer if it still faults. **★★ B2 VALIDATED on GB10 (2026-08-01, with the mem-free fix): RUN_EXIT=0, coherent, first 13 generated tokens MATCH the vLLM-Marlin golden EXACTLY** (`22345 83 290 350 674 330 5541 966 340 9626 377 15360 81` — the best Laguna-NVFP4 correctness yet, W4A16 matching vLLM's config). **Steady-state decode 0.10 s/tok = ~10 tok/s** (steps 10-17 all 0.10; the TPOT-0.56 average is warmup-polluted — the DevicePool warms over ~9 decode steps then reuses). vs the GEMV path's 6.7 tok/s = **~1.5× faster; the gap to vLLM 18.8 closes from ~3× to ~1.9×.** Memory flat (7.9 GiB host RSS — the fp4-original free worked; it also fixed the first-forward fault). Still `VT_LAGUNA_MARLIN_MOE=1` default-OFF. TO DONE: move the lazy Marlin-resident build (216s first-forward, 48L×256E repack) to model-LOAD time → clean warm A/B + ncu → flip default-ON → matrix/roadmap. Remaining ~1.9×: vLLM graphs its decode (ours still eager) — decode CUDA-graph is the next lever. **REPRODUCED 3× (reproduction gate MET): GB10 runs deterministic — first 18-20 tokens byte-identical, steady-state 0.10 s/tok confirmed each — so the ~10 tok/s + golden-match is gated, not a single sample.** **#234 item (1) — load-time resident-build LANDED (`LagunaBuildMarlinResidents`, called from the example after load; mirrors vLLM process_weights_after_loading): builds all 48L×256E Marlin residents at LOAD so the repack is not a first-token TTFT spike. Fixed an anon-namespace linkage bug (public fn was defined with internal linkage → moved outside the anon namespace); BUILD CLEAN + links on GB10 sm_121a, default-OFF. Runtime prewarm-fires-at-load timing UNVERIFIED this session (repeated ssh-drops ate the run capture); the forward's lazy build is the validated fallback so it cannot regress. Owed: one clean run to confirm the build moved to load + then flip default-ON.** **★★ DONE (2026-08-01): Marlin is now the UNCONDITIONAL DEFAULT (`LagunaMarlinMoeEnabled` default-ON; `=0` is a code-level A/B opt-out no user needs) — "it just works" with NO env. Confirmed in a no-env GB10 run captured via tmux: `MARLIN residents built at load in 238.4s`, prefill 14.78s (build moved OUT of first-forward), golden-matching ids, steady-state 0.10 s/tok = ~10 tok/s (4th reproduction), RSS ~5-8 GiB. So a default Laguna-NVFP4 load on GB10 gets vLLM's own W4A16 Marlin decode (~10 tok/s, ~1.9× from vLLM 18.8) with zero flags. The 238s load-time repack is a one-time cost (mirrors vLLM process_weights_after_loading); optimizing its 48×256 per-expert sync count is a follow-up. Residual to 18.8 = decode CUDA-graph (deferred; user refocusing on DeepSeek next).** Post-lever-1 nsys: the remaining ~4× is HOST-SYNC-bound — 22,115 `cudaStreamSynchronize` (78.6% of API time, ~2,760/token, the per-GEMM `DrainQueue`), GPU kernels fast. Remaining levers: grouped W4A4 MoE (design input: `vt::MoeGroupedGemmNvfp4` is W4A16, so true-W4A4 grouped needs a new fp4×fp4 op or the `use_a16` mode + expert-stacking — needs a spike), device-resident decode (RECOMMENDED — the current forward is host-style so every GEMM drains; keep activations on-device, drain once/step; reuse qwen3_5's `Dev`/`Nvfp4Dev`/`ResidentNvfp4`/device-SwiGLU machinery; kills the 22k syncs; converges with the pending GGUF #228 and lifts both quant paths), decode CUDA-graph. Binding number needs a clean 2-3× re-run. See `docs/BENCHMARKS.md` + the spec N5 plan. See `docs/BENCHMARKS.md` `CLAIM-LAGUNA-VLLM-NVFP4`. Prior W7 nsys attribution: host-orchestration-bound, levers ranked (spec `laguna-s21-w7-speed-2026-07-31.md`, ledger `CLAIM-LAGUNA-W7-SPEED`). Prior RUNNABLE + FAST DECODE (W6, 2026-07-31): a per-layer K/V cache + single-token incremental decode replaces W5's O(n²) STATELESS full-recompute — TOKEN-IDENTICAL (byte-equal ids, md5 match, == the W5 golden) and 5.05× faster per token: decode 3.33 → 0.66 s/tok on the real 3-shard UD-Q4_K_XL GGUF (GB10, `--gpu`, keep-quant), same "The capital of France is" → " Paris.\n\nThe user is seeking a detailed explanation of the concept of \"cultural capital\"…". `LagunaKvCache` (mirrors `DeepseekV4KvCache`, MLA-latent → GQA multi-head K/V) caches post-QK-RMSNorm/post-RoPE K + raw V at f32 (bit-exact by construction: RoPE/QK-norm are position-only and attention is causal). MIXED attention handled per-layer: 12 GLOBAL layers grow the cache unbounded (full causal); 36 SLIDING-WINDOW-512 layers EVICT the oldest rows beyond the 512 window (gemma2/3 `is_sliding`), capping their K/V. `LagunaForwardGgufCached` + shared `LagunaAttention`/`LagunaFfnBlock` helpers used by BOTH forwards (identical float ops — the recompute path's ids are unchanged after the refactor); `examples/laguna_gen --stateless` forces the W5 recompute for the A/B gate. No cache bug: bit-exact on the first run. Next speed: grouped-expert GEMM + device-resident decode (both in-tree from ds4). See `.agents/specs/laguna-s21-w6-2026-07-31.md`. Prior RUNNABLE (W5, 2026-07-31): our engine greedy-generates COHERENT text on the REAL 3-shard UD-Q4_K_XL GGUF (GB10, keep-quant). `laguna-gen` "The capital of France is" → " Paris.\n\nThe user is seeking a detailed explanation of the concept of \"cultural capital\" as developed by French soci…" — the FIRST token is "Paris.", matching the llama.cpp-Poolside reference on the identical bytes. Multi-shard GGUF reader (LagunaGgufCtx routes each of 814 tensors to its shard; shard-1 = header only) + keep-quant tower (attn/dense/shared/experts/lm_head stay Q8_0/Q4_K/Q5_K COMPRESSED, consumed via `vt::MatmulBT`; norms/router/bias/embed → f32) + `LagunaForwardGguf` (the f32 composition with the ~9 GEMM sites swapped to keep-quant Gemm/GemmRowSlice, ds4 precedent) + `examples/laguna_gen`. Real GGUF metadata verified: dual-RoPE freq_base 500000/10000, dims 64/128, YaRN factor 32, sigmoid ungrouped-noaux router (scale 2.5), per-layer Q-head [48 global/72 sliding], per-head softplus out-gate, QK-RMSNorm. Load 20.6s, peak 71 GiB (fits 119 pool). Prior W4 IN PROGRESS (2026-07-31): 73.4 GiB UD-Q4_K_XL GGUF FETCHED + read authoritatively (814 tensors); 3 CPU-verified fidelity corrections grounded in the real GGUF + llama.cpp — per-head QK-RMSNorm (`attn_q/k_norm`, the scope MISSED it), GGUF-authoritative dual-RoPE mscale (llama.cpp `yarn_attn_factor·(1+0.1·ln(factor))`, factor 32 not HF 128), separate `ffn_gate/up_exps`. Keep-quant tower materialization + `ForwardGguf` + the real-model greedy run vs llama.cpp-laguna same-quant oracle = W5 close. Prior: W3 REAL host-reference forward + 3 new ops (`laguna_ops.cpp`, CPU `-Werror` clean, `test_laguna_scaffold` unit-gated)** | Poolside Laguna: 48 layers (12 global + 36 sliding-window-512), 256 routed top-10 + 1 shared expert, per-head **softplus attention output gate**, sigmoid `noaux_tc` router, dual per-layer RoPE (YaRN full-attn / plain sliding), GQA 8 KV / 128 head-dim, 1M ctx. **W3 (2026-07-31):** the 3 genuinely-NEW small host ops landed in `laguna_ops.cpp` — per-head softplus attn out-gate (`LagunaSoftplusHeadGate`), ungrouped sigmoid-noaux router (`LagunaUngroupedRouterTopK`, ds3 noaux_tc MINUS the group step + tie-break razor), dual per-layer RoPE cos/sin builders (`BuildLaguna{FullYarn,Sliding}CosSin`, reusing the pinned YaRN inv_freq over the partial-64 dims); `LagunaModel::Forward` is now a REAL runnable host-reference composition (variable-Q-head GQA + dual RoPE + sliding-window mask + softplus gate + dense L0 / ungrouped-MoE L1..47 + untied lm_head) replacing the `VT_CHECK(false)` stub; `test_laguna_scaffold` **8/8·166** (softplus math, router selection+tie-break RED-first, dual-RoPE bit-match, variable-Q-head shapes, forward composition on synthetic weights), `test_model_registry` 24/24. **W2 (2026-07-30):** registered, `ParseLagunaParams`, GGUF `blk.N.*` name-map + UD-Q4_K_XL quant-mix (Q4_K/Q5_K/Q6_K/Q8_0 ALL already decoded → ZERO new kernel). **W1 oracle DECISION:** vLLM NATIVE `laguna.py` (in pin → config constructs); dual-oracle = vLLM-NVFP4/-FP8 (fits GB10 119 GiB; BF16 235 GiB does NOT) + llama.cpp-Q4_K token-exact. ~85–90% reuse (ds4-MoE + Gemma-sliding + OLMo-3-dual-rope + Q4_K keep-quant, ALREADY landed). DEFERRED (W4): GGUF keep-quant tower materialization + device/paged production forward (loaders still LOUDLY throw) + strict dual-oracle greedy gate on a fetched checkpoint + `poolside_v1` parser. See `.agents/specs/laguna-s21-w3-2026-07-31.md` (+ W1/W2 `laguna-s21-w1w2-2026-07-30.md`, W0 `laguna-s21-scope-2026-07-30.md`). **Decode attention-glue fusion LANDED (2026-08-02, `CLAIM-LAGUNA-GLUE-FUSED`, default-ON `VT_LAGUNA_GLUE_FUSED`, `=0` A/B):** BYTE-EXACT L1 (softplus out-gate → `DecodeAttnCombineKernel` store) + L4 (residual-Add+RMSNorm pairs → the shared `vt::FusedChain(kFusedAddRmsNormStd)` seam) on the resident decode-graph — same-binary A/B ids byte-identical (159/159 @160), paging-immune nsys steady decode **−4.2% GPU-busy (28.90→27.69 ms/step), −120 graph nodes/step (−10%)**, wall drop_caches-tied (no regression). C shared-into-MoeCombine SKIPPED (Laguna's bf16 `MoeCombine` → not byte-exact); L2 qk-norm+RoPE preamble DEFERRED (needs a device-position kernel variant). See BENCHMARKS.md `CLAIM-LAGUNA-GLUE-FUSED`. **On-device greedy sample LANDED (2026-08-02, `CLAIM-LAGUNA-ONDEV-SAMPLE`, default-ON `VT_LAGUNA_ONDEV_SAMPLE`, `=0` A/B):** the resident decode graph used to Synchronize, return the whole `[100352]` logits, and argmax on the HOST between replays (+ host embed-gather of the next token) — the off-framework "born-on-host" seam the decode-framework-routing audit flagged. Now BOTH run ON-DEVICE inside the captured graph: `vt::GreedyArgmax` (lowest-index tie = the exact host winner) → 1-elem device token buffer, + a new capture-safe `embed_gather` kernel gathers the next input embedding from it (the stock `vt::Embedding` is NOT capture-safe: per-call event-sync + D2H ring). BYTE-EXACT (160-id stream identical `=0`/`=1` on `~/laguna-xs-nvfp4`) + faster: paired drop_caches decode wall **+0.28% median** (8/8 reps ≥0; removes ~150 us/step host argmax) at GPU-busy parity (nsys 2-length 27.44→27.42 ms/step). Aligns Laguna decode with vLLM on-device sampling. **Lever 2 (lm_head GEMV DRAM eff) MEASURED, NOT landed:** `[M=1,100352,2048]` bf16 = **170 GB/s (2.41 ms)** = ~91% of the cuBLAS M=1×large-N reference (~187 GB/s / 2.2 ms) — at the M=1 practical floor (the 273 GB/s ceiling is streaming-only, unreachable for a once-read GEMV); ≤0.7%-of-step headroom needs a reduction reorder (near-tie re-gate) ⇒ not chased, per prior "lm_head optimal". See BENCHMARKS.md `CLAIM-LAGUNA-ONDEV-SAMPLE`. **MoE add_rms_norm fold LANDED (2026-08-02, `CLAIM-LAGUNA-MOE-ADDNORM`, default-ON `VT_LAGUNA_MOE_ADDNORM_FUSED`, `=0` A/B):** the glue-fused MoE tail ran its residual update as TWO graph nodes — `vt::Add(hidden,routed)` [`AddKernel`] + `FusedChain(kFusedAddRmsNormStd)` [shared-add+RMSNorm, `RmsNormRowKernel`] — now ONE `fused_add2_rmsnorm` device node/MoE-layer (`hidden=(hidden+routed)+shared; hn=rms_norm(hidden)*w`). BYTE-EXACT (IEEE add commutes + the identical 256-thread shared-tree norm reduction; 160-id stream byte-identical `=0`/`=1` on `~/laguna-xs-nvfp4`) + faster: **−39 `AddKernel` graph nodes/step** (2.63ms→0 over 69 steps), paging-immune nsys 2-length **~−46 us/tok GPU (27339→27293)**, nsys wall **+0.4% (34.00→34.14 tok/s @70-tok)**. Small (byte-exact node-count trim on the graph-captured, GPU-bound decode; the dominant ~72% cost is the bf16 projection GEMVs — see the Lever-B negative in BENCHMARKS.md). See BENCHMARKS.md `CLAIM-LAGUNA-MOE-ADDNORM`. **Shared expert kept fp4 LANDED (2026-08-03, `CLAIM-LAGUNA-SHARED-FP4`, default-ON `VT_LAGUNA_SHARED_FP4`, `=0` A/B):** the XS-NVFP4 shared expert was DEQUANTIZED to bf16 at load (`LnLoadSharedExpertBf16`) → the M=1 decode GEMV read 4× the DRAM bytes of vLLM (which keeps it fp4). Now kept fp4-resident and routed through the SAME Marlin W4A16 single-expert (num_experts=1) grouped GEMM the routed experts win on (`dense_nvfp4::GateUpFusedMarlinD`+`MatmulNvfp4MarlinD`); the decode GEMV drops to router-ONLY (`moe.router`), shared gate/up/down go fp4. ADDITIVE new `laguna_shared_fp4.cpp` re-reads the on-disk fp4 from the gen driver before shard release (does NOT touch SACRED `laguna_weights.cpp`); bf16 shared KEPT for the T>1 prefill. NEAR-TIE (fp4≠bf16): coherent, first-20 ids == documented golden, byte-identical to bf16 for ~85 tokens then diverges; **DISTRIBUTIONAL GATE PASS 40/40** (ours' first-40 ids ∈ vLLM's 8-run greedy candidate set; vLLM XS-greedy is bf16-non-det, 8 unique of 8). FASTER: paging-immune nsys 2-length **GPU 27.24→26.53 ms/step (−2.6%)**, wall drop_caches **35.8→36.3 tok/s (+1.4%, fp4 wins all 3 reps)**; shared-expert kernel bucket ~1.68→~0.90 ms/step (halved); vs vLLM ~43 tok/s 83.3%→84.4%; RSS 22.2→22.1 GiB (freed the decode-only fused router-shared projection). Modest by design — XS's shared expert is small (`shared_expert_intermediate_size==moe_intermediate_size==512`). Default-ON per parity (matches vLLM's fp4 shared). See BENCHMARKS.md `CLAIM-LAGUNA-SHARED-FP4`. **qk-norm+RoPE preamble fusion LANDED (2026-08-03, `CLAIM-LAGUNA-PREAMBLE-FUSED`, default-ON `VT_LAGUNA_PREAMBLE_FUSED`, `=0` A/B):** closes the `CLAIM-LAGUNA-GLUE-FUSED` L2 deferral — the decode graph ran the per-layer attention preamble as FOUR under-occupied M=1 nodes (`rms_norm_seq(q)`+`rms_norm_seq(k)`+`rope_from_cache_g(q)`+`rope_from_cache_g(k)`); now ONE capture-safe `fused_qk_norm_rope_g` node/layer (`FusedQkNormRopeGKernel`, one block/head, reads the decode position from DEVICE `*pos_buf`, handles the per-layer dual-RoPE 64/128 + `Hq` 48/64). BYTE-EXACT BY CONSTRUCTION: it replicates the composed path's f32 MEMORY round-trip (Phase A 256-thread Σx² == `RmsNormSeqKernel`; Phase B the same `(x*inv)*w` store; `__syncthreads`; Phase C the `RopeFromCacheGKernel` rope read back) — an earlier register-only recompute was numerically-equivalent but diverged at a token-110 near-tie via compiler fma-contraction; the memory boundary forces bit-identity. 160-id stream byte-identical `=0`/`=1` on `~/laguna-xs-nvfp4` (determinism verified `=0`×3/`=1`×3 each run-to-run identical). FASTER: preamble norm+rope kernels **160→40 launches/tok, 326→154 us/tok (−0.17 ms/step)**; all decode-scaling kernels 26.53→26.37 ms/step; wall drop_caches **36.42→36.64 tok/s (+0.6%, fused wins all 3 paired reps)**; vs vLLM ~43 84.7%→85.2%. Modest (preamble ~1.2% of the 26.5 ms/step decode; the dominant cost stays the bf16 projection GEMVs at cuBLAS parity) — a byte-exact graph-node/launch trim (the glue-fusion residual mechanism). Default-ON per parity. See BENCHMARKS.md `CLAIM-LAGUNA-PREAMBLE-FUSED`. **W7 two-front pass LANDED (2026-08-03, `CLAIM-LAGUNA-W7-DECODE`):** FRONT 1 — the example driver logged `[gen] step N …(RSS)` EVERY decode step, and the RSS arg calls `CurResidentGiB()` (a `/proc/self/status` read) + an unbuffered stderr write in the GPU-idle gap between replays; guarded behind `VT_LAGUNA_STEP_LOG` (default OFF) + added a `decode_wall` line (TRUE end-to-end throughput incl. per-step gaps) next to the gap-free `decode_hp`. Since the fprintf sat OUTSIDE the `s0→s1` timer, `decode_hp` was ALREADY honest; with the log off `decode_wall == decode_hp` (within 0.001 tok/s, every LOG_OFF rep) and the recovered host tax is only ~0.1% (drop_caches noise floor). CONCLUSION: the ~86% gap to vLLM 43 is genuine device compute, NOT a harness artifact. FRONT 2 — `VT_LAGUNA_MOE_ONECAST` (default ON): a MoE layer cast the same `hn[1,H]` f32→bf16 THREE times (router GEMV + routed Marlin + shared Marlin); now cast ONCE into a persistent buffer and reuse (`CastHnBf16`/`GemmBf16Pre` + optional pre-cast param on both `…Into` helpers). BYTE-EXACT (deterministic truncation; `=1` vs `=0` byte-identical 300-tok ids); `CastBf16` **200→122 nodes/step (−78 = 2×39 MoE layers)**, GPU-busy parity within nsys noise, decode_hp +0.29%. Combined (onecast on + log off) **36.97 tok/s = 86.0% of vLLM-NVFP4 43** (from 36.64/85.2%). See BENCHMARKS.md `CLAIM-LAGUNA-W7-DECODE`. **Tail-fold follow-up LANDED (2026-08-03, `CLAIM-LAGUNA-TAIL-FUSED`, default-ON `VT_LAGUNA_TAIL_FUSED`, `=0` A/B):** a fresh node-ranking of the baseline decode graph found the routed-MoE `CastF32` as the one clean byte-exact fold left; it folds into the trailing `fused_add2_rmsnorm` via a new bf16-x1 sibling kernel (`AddAdd2RmsNormStdBf16Kernel` — `MoeCombine` writes bf16 straight to a persistent buffer, widened in-kernel by `__bfloat162float`). BYTE-EXACT (`=1` vs `=0` byte-identical 160-tok ids), `CastF32` **78→39 nodes/step**, total graph nodes **919→880**, GPU-busy parity; decode_hp a WASH (median +0.14% / mean −0.04%, at the drop_caches noise floor). Lands on the deterministic node-count basis (like onecast/preamble/addnorm), NOT a wall win; combined headline UNCHANGED **36.97 tok/s = 86.0%**. The ranking confirms the byte-exact decode-tail fold tier is now essentially EXHAUSTED (residual tail = already-folded norms + attention compute + cuBLAS-adjacent router/topk + ported-Marlin `MoeAlign`/`SiluAndMul`/`MoeCombine`); the gap to vLLM 43 is genuine device compute at the practical ceiling. See BENCHMARKS.md `CLAIM-LAGUNA-TAIL-FUSED`. **KERNEL-EFFICIENCY tier (2026-08-03, `VT_LAGUNA_FAST_NORM` default ON + f32 ext of `VT_RMSNORM_DECODE_FAST`):** the fold tier was exhausted but the residual-stream norm KERNELS were still under-occupied — `ncu` on the shipped `<<<1,256>>>` `AddAdd2RmsNormStdBf16`/`RmsNormRow` decode norms: `launch__waves_per_multiprocessor≈0.00`, `sm__throughput≈0.06%` (one 256-thread block on 1 SM of ~100+, latency-bound). Porting the PROVEN bit-identical `RmsNormRowFastKernel` structure (1024-thread float4 memory passes; 256-strided-partial + tree reduction reproduced byte-for-byte) to the f32 kernels cut each **286→~155 µs/tok (1.85×)**, **byte-exact** (160-tok ids identical `=1`vs`=0`; the f32 fix vs the bf16 sibling: store `v` not `v²` and square in the reduction so nvcc emits shipped's `acc += v*v` **fma** — a pre-squared f32 `v²` is not exact and flipped an XS near-tie at tok 108). **−0.81% decode-step GPU time** (paging-immune 70-vs-20 2-length diff, 26192→25980 µs/step); wall-clock ON/OFF overlap (noise floor). Residual: the byte-exact 256-strided reduction can't reach vLLM's per-kernel norm floor (~2.4× vLLM) without breaking byte-exactness → that remainder is byte-exactness-BLOCKED. See BENCHMARKS.md `CLAIM-LAGUNA-FAST-NORM`. **Router top-k warp-shuffle LANDED (2026-08-03, `CLAIM-LAGUNA-TOPK-SHFL`, default-ON `VT_LAGUNA_TOPK_SHFL`, `=0` A/B): BYTE-EXACT** — an nsys 2-length rank of the remaining small kernels (past the at-parity `gemvx` projection GEMVs ~69% of step + Marlin MoE) put the router `SigmoidTopKKernel` top (415 µs/step); `ncu` showed it `<<<1,256>>>` at `waves≈0.000`/`sm≈0.2%` — pure latency (8 serially-dependent rounds × a ~10-sync `sh[256]` argmax tree). New `SigmoidTopKShflKernel` reduces each round by warp-shuffle argmax (2 syncs/round; argmax over the total order is associative ⇒ SAME winner) → **`SigmoidTopK` 414.6→248.8 µs/step (1.67×)**, decode-step GPU **−0.57%** (26.018→25.869 ms/step), 37.39→37.49 tok/s decode_hp (**87.2% of vLLM-NVFP4 43**); 160-id stream byte-identical `=1`vs`=0`. **NOT landed — norm warp-shuffle (`VT_LAGUNA_NORM_SHFL`):** a near-tie register-accumulate+shuffle reduce for the Laguna `AddAdd2RmsNormStd{,Bf16}Fast` norms PASSED the distributional gate (coherent, in-set 38/40 = baseline, one near-tie fork at pos 37) and was −19.3% per-kernel (`AddAdd2RmsNormStdBf16` 150.3→121.3 µs/step) BUT washed at whole-step (0.6% of step; +0.02% within noise) — a near-tie fork isn't justified by a below-noise gain, so it was dropped. The small-kernel norm tail is at its occupancy floor; the decode step is dominated by the at-parity projection GEMVs. See BENCHMARKS.md `CLAIM-LAGUNA-TOPK-SHFL`. **Shared-expert 2-stream overlap LANDED (2026-08-03, `CLAIM-LAGUNA-SHARED-AUX`, default-ON `VT_LAGUNA_SHARED_AUX`, `=0` A/B):** mirror of vLLM's `MULTI_STREAM_OVERLAPPED` — in `LagunaGraph::RunChain` the fp4-shared arm's shared expert is EARLY-forked onto a second CUDA stream from the post-attn hidden `hn` BEFORE the router GEMV (aux reads `hn` f32 + does its own byte-identical cast; scratch from `AuxPool`), overlapping router+`sigmoid_topk`+routed grouped GEMM, joined before the combine — the SAME machinery the 35B ships default-ON (ENG-MOE-SHARED-AUX, runs inside the captured graph). This is the EARLY fork the prior fused-`router_shared_gu` attempt (`89e0d074`, −0.35% wash) could not reach. Capture-safe (aux stream+2 events in the ctor; gstate-0 warm-run builds residents + warms `AuxPool`). **BYTE-EXACT** (`=1`vs`=0` byte-identical 63-tok ids). REAL concurrency: nsys `--cuda-graph-trace=node` 20↔70 sum-vs-union → OVERLAP **2.34 ms/step** (SUM/UNION 1.092) vs `=0`'s 0.0004 ms; net GPU-busy wall **26.213→25.467 ms/step (−2.9%, 38.15→39.27 tok/s)**, wall @200 37.08→37.93 (+2.3%). Netdecode a real image std::string prompt_image_path; // diagnostic: run an image through the vision tower + std::string cond_image_path; // route an image through the ENCODER vision path + // (merged scatter into prompt_embeds + DeepStack) std::vector ref_image_paths; std::string ref_video_prefix, ref_audio_path; // The served checkpoint PARTITION. Community GGUF/NVFP4 files strip the release @@ -234,6 +237,7 @@ int main(int argc, char** argv) { else if (f == "--decode-latent") decode_latent_path = Need(argc, argv, ++i, f); else if (f == "--roundtrip") roundtrip_path = Need(argc, argv, ++i, f); else if (f == "--prompt-image") prompt_image_path = Need(argc, argv, ++i, f); + else if (f == "--cond-image") cond_image_path = Need(argc, argv, ++i, f); else if (f == "--device") device_name = Need(argc, argv, ++i, f); else if (f == "--encoder") encoder_path = Need(argc, argv, ++i, f); else if (f == "--prompt") prompt = Need(argc, argv, ++i, f); @@ -595,13 +599,61 @@ int main(int argc, char** argv) { const vllm::tok::Tokenizer tokenizer = tokenizer_path.empty() ? vllm::tok::Tokenizer::FromGguf(ef) : vllm::tok::Tokenizer::FromHfJson(tokenizer_path); - const std::vector ids = tokenizer.Encode(prompt); + std::vector ids = tokenizer.Encode(prompt); VT_CHECK(!ids.empty(), "minimax-h3-gen: the prompt tokenized to nothing"); std::cerr << " prompt tokens = " << ids.size() << "\n"; - // DIAGNOSTIC (env-gated): dump the raw prompt token ids so the tokenization - // can be diffed against upstream `minimax_h3_text_only_ids` (verbatim prompt, - // add_special_tokens=False). A BOS/template mismatch shifts every text row and - // feeds the 32B tower a different string -> different conditioning. + + // --cond-image routes a reference image through the ENCODER VISION PATH + // (upstream _encode, encoder.py:1064-1101): the vision tower's MERGED features + // masked_scatter into inputs_embeds at the image-pad positions, and its 3 + // DeepStack blocks inject into the first N text layers. This is the residual + // #86 left open — the vision features now REACH the DiT via prompt_embeds. + std::vector visual_mask; // 1 at each image-pad row + std::vector> deepstack; // 3 x [nm, hidden] taps + std::vector merged; // [nm, hidden] merged features + std::array vgrid{1, 0, 0}; + int64_t vsmerge = 2; + const bool have_vision = !cond_image_path.empty(); + if (have_vision) { + VT_CHECK(device_name == "cuda", + "minimax-h3-gen: --cond-image needs --device cuda (the vision tower is " + "device-resident)"); + const vllm::multimodal::Qwen3VLVisionConfig vcfg = vllm::MiniMaxH3EncoderVisionConfig(); + const vllm::multimodal::Qwen3VLVisionWeights vw = vllm::LoadQwen3VLVisionFromGguf(ef, vcfg); + vsmerge = vcfg.spatial_merge_size; + int64_t cih = 0, ciw = 0; + const std::vector rgb = ReadPpmAsHwcU8(cond_image_path, &cih, &ciw); + std::cerr << " cond-image " << ciw << "x" << cih << "\n"; + vllm::multimodal::Qwen3VLProcessorConfig pcfg; // patch16/temporal2/merge2/0.5-norm + pcfg.merge_size = static_cast(vsmerge); + const vllm::multimodal::Qwen3VLImageProcessor proc(pcfg); + const vllm::multimodal::ImageKwargs kw = proc.ProcessImage(rgb.data(), cih, ciw); + vgrid = kw.image_grid_thw; + vt::Backend& vbackend = vt::GetBackend(vt::DeviceType::kCUDA); + vllm::multimodal::Qwen3VLVisionCapture cap; + (void)vllm::multimodal::Qwen3VLVisionForward(kw.pixel_values_bf16, vgrid, vw, vcfg, + vbackend, &cap); + merged = std::move(cap.merger_out); + deepstack = std::move(cap.deepstack_out); + const int64_t nm = vgrid[0] * vgrid[1] * vgrid[2] / (vsmerge * vsmerge); + std::cerr << " cond-image: grid=[" << vgrid[0] << "," << vgrid[1] << "," << vgrid[2] + << "] merged=" << nm << " deepstack=" << deepstack.size() << "\n"; + // Prepend a vision block , then expand + // the single image_pad into nm image_token_id copies (the mm processor). + std::vector pre = {pcfg.vision_start_token_id, pcfg.image_token_id, + pcfg.vision_end_token_id}; + pre.insert(pre.end(), ids.begin(), ids.end()); + std::vector> placeholders; + ids = vllm::multimodal::ExpandImagePlaceholders( + pre, pcfg.image_token_id, static_cast(vsmerge), + {{vgrid[0], vgrid[1], vgrid[2]}}, &placeholders); + VT_CHECK(!placeholders.empty(), + "minimax-h3-gen: cond-image placeholder expansion produced none"); + } + + // DIAGNOSTIC (env-gated): dump the (possibly expanded) token ids so the + // tokenization can be diffed against upstream. A template mismatch shifts + // every text row and feeds the 32B tower a different string. if (const char* dd = std::getenv("VT_H3_DUMP_INPUTS")) { if (std::FILE* fp = std::fopen((std::string(dd) + "/prompt_token_ids.i32").c_str(), "wb")) { std::fwrite(ids.data(), sizeof(int32_t), ids.size(), fp); @@ -611,12 +663,47 @@ int main(int argc, char** argv) { std::cerr << "\n"; } } - const std::vector embeds = vllm::MiniMaxH3EncoderEmbedTokens(enc, ids); - // Text-only: all three M-RoPE axes are the token index. + const int64_t seq = static_cast(ids.size()); + std::vector embeds = vllm::MiniMaxH3EncoderEmbedTokens(enc, ids); std::vector pos(static_cast(3 * seq)); - for (int64_t a = 0; a < 3; ++a) { - for (int64_t s = 0; s < seq; ++s) pos[static_cast(a * seq + s)] = s; + if (!have_vision) { + // Text-only: all three M-RoPE axes are the token index. + for (int64_t a = 0; a < 3; ++a) { + for (int64_t s = 0; s < seq; ++s) pos[static_cast(a * seq + s)] = s; + } + } else { + // masked_scatter the merged features into the image-pad rows + build the + // visual position mask (upstream `inputs_embeds.masked_scatter(image_mask, + // image_embeds)` + `_get_placeholder_mask`). + const int32_t IMG = vllm::multimodal::Qwen3VLProcessorConfig{}.image_token_id; + visual_mask.assign(static_cast(seq), 0); + const int64_t hidden = ec.hidden_size; + int64_t vi = 0, off = -1; + for (int64_t s = 0; s < seq; ++s) { + if (ids[static_cast(s)] != IMG) continue; + if (off < 0) off = s; + visual_mask[static_cast(s)] = 1; + VT_CHECK((vi + 1) * hidden <= static_cast(merged.size()), + "minimax-h3-gen: merged vision rows < image-pad tokens"); + for (int64_t i = 0; i < hidden; ++i) + embeds[static_cast(s * hidden + i)] = + merged[static_cast(vi * hidden + i)]; + ++vi; + } + VT_CHECK(vi * hidden == static_cast(merged.size()), + "minimax-h3-gen: merged vision rows != image-pad tokens"); + // M-RoPE positions. Qwen3VLGetRopeIndex is byte-equivalent to H3's own + // _get_rope_index for a single-frame image (t==1): text runs sequentially, + // the image block takes the 3D vision grid, and the next text advances by + // max(llm_h, llm_w). Layout is [3, seq] flattened as [axis*seq + s]. + vllm::multimodal::MmImageSpan span{off, {vgrid[0], vgrid[1], vgrid[2]}}; + int64_t delta = 0; + const std::vector p3 = + vllm::multimodal::Qwen3VLGetRopeIndex(ids, {span}, vsmerge, &delta); + VT_CHECK(static_cast(p3.size()) == 3 * seq, + "minimax-h3-gen: rope index produced the wrong count"); + for (size_t i = 0; i < pos.size(); ++i) pos[i] = static_cast(p3[i]); } vt::Device enc_dev{}; if (device_name == "cuda") { @@ -627,9 +714,10 @@ int main(int argc, char** argv) { if (enc_dev.type != vt::DeviceType::kCPU) eq = eb.CreateQueue(); const vllm::MiniMaxH3EncoderDeviceWeights staged = vllm::StageMiniMaxH3EncoderWeights(eq, enc); - std::cerr << " encoding prompt...\n"; - encoded_prompt = - vllm::MiniMaxH3EncoderTextForwardDevice(eq, ec, staged, embeds, pos.data(), seq); + std::cerr << " encoding prompt" << (have_vision ? " (vision-conditioned)" : "") << "...\n"; + encoded_prompt = vllm::MiniMaxH3EncoderTextForwardDevice( + eq, ec, staged, embeds, pos.data(), seq, + have_vision ? visual_mask.data() : nullptr, deepstack); std::cerr << " conditioning = [" << seq << ", " << ec.hidden_size << "]\n"; // Persisting the conditioning makes a checkpoint A/B CONTROLLED: two DiTs // can then be compared on byte-identical text conditioning instead of two diff --git a/include/vllm/model_executor/models/minimax_h3.h b/include/vllm/model_executor/models/minimax_h3.h index 7a82289d..0774c4f4 100644 --- a/include/vllm/model_executor/models/minimax_h3.h +++ b/include/vllm/model_executor/models/minimax_h3.h @@ -1065,10 +1065,22 @@ MiniMaxH3EncoderDeviceWeights StageMiniMaxH3EncoderWeights( // its ggml blocks with no dequantization. `positions` is [3, seq] (the M-RoPE // temporal/height/width axes); for a pure text prompt all three are the token // index. Returns [seq, hidden] f32. +// +// DeepStack (image/video conditioning): `visual_pos_mask` is [seq] (1 at each +// visual-token row) and `deepstack` is one [num_visual, hidden] block per tap. +// After each of the FIRST `len(deepstack)` decoder layers, each block is ADDED to +// the masked rows — the device mirror of MiniMaxH3EncoderTextForward's DeepStack +// and of upstream `MiniMaxH3Qwen3VLTextModel._deepstack_process` (encoder.py:770-800, +// `hidden_states[visual_pos_masks] += visual_embeds`). Text-only prompts pass the +// defaults (no mask, no blocks) and the path is byte-identical to before. The +// MERGED-feature masked_scatter into `inputs_embeds` is the CALLER's job (upstream +// `_encode` does it on inputs_embeds before the tower runs); this forward consumes +// the already-scattered stream, exactly like the host reference. std::vector MiniMaxH3EncoderTextForwardDevice( vt::Queue& queue, const MiniMaxH3EncoderConfig& config, const MiniMaxH3EncoderDeviceWeights& weights, const std::vector& inputs_embeds, - const int64_t* positions, int64_t seq); + const int64_t* positions, int64_t seq, const uint8_t* visual_pos_mask = nullptr, + const std::vector>& deepstack = {}); MiniMaxH3EncoderQuantWeights LoadMiniMaxH3EncoderFromGguf(const GgufFile& file, int64_t max_layers = 0); diff --git a/src/vllm/model_executor/models/minimax_h3_encoder_device.cpp b/src/vllm/model_executor/models/minimax_h3_encoder_device.cpp index 56e83284..00ef5ce0 100644 --- a/src/vllm/model_executor/models/minimax_h3_encoder_device.cpp +++ b/src/vllm/model_executor/models/minimax_h3_encoder_device.cpp @@ -103,7 +103,8 @@ std::vector BuildEncoderRopeCache(const int64_t* positions, int64_t seq, std::vector MiniMaxH3EncoderTextForwardDevice( vt::Queue& queue, const MiniMaxH3EncoderConfig& config, const MiniMaxH3EncoderDeviceWeights& weights, const std::vector& inputs_embeds, - const int64_t* positions, int64_t seq) { + const int64_t* positions, int64_t seq, const uint8_t* visual_pos_mask, + const std::vector>& deepstack) { vt::Backend& backend = vt::GetBackend(queue.device.type); Dev d{backend, queue}; @@ -214,6 +215,34 @@ std::vector MiniMaxH3EncoderTextForwardDevice( } vt::MatmulBT(d.q, attn_out.t(), act.t(), weights.Get(p + "mlp.down_proj.weight")); vt::Add(d.q, h.t(), h.t(), attn_out.t()); + + // DeepStack: ADD the visual features into the visual-token rows, for the FIRST + // len(deepstack) layers only (encoder.py:792-799; host mirror + // MiniMaxH3EncoderTextForward). Upstream `_deepstack_process` does + // `hidden_states[visual_pos_masks, :] += visual_embeds`; we scatter the block + // into a [seq, hidden] additive buffer at the masked rows and add on device. + // Text-only prompts leave `deepstack` empty and this never runs. + if (layer < static_cast(deepstack.size())) { + VT_CHECK(visual_pos_mask != nullptr, + "minimax_h3 encoder device: deepstack embeds require a visual position mask"); + const std::vector& embeds = deepstack[static_cast(layer)]; + std::vector add_host(static_cast(seq * hidden), 0.0f); + int64_t visual_index = 0; + for (int64_t s = 0; s < seq; ++s) { + if (!visual_pos_mask[s]) continue; + VT_CHECK((visual_index + 1) * hidden <= static_cast(embeds.size()), + "minimax_h3 encoder device: deepstack block has fewer rows than masked positions"); + for (int64_t i = 0; i < hidden; ++i) { + add_host[static_cast(s * hidden + i)] = + embeds[static_cast(visual_index * hidden + i)]; + } + ++visual_index; + } + VT_CHECK(visual_index * hidden == static_cast(embeds.size()), + "minimax_h3 encoder device: deepstack block row count != masked positions"); + DBuf add_dev(d, DType::kF32, {seq, hidden}, add_host.data()); + vt::Add(d.q, h.t(), h.t(), add_dev.t()); + } } // NO final RMSNorm: H3 reads the UNNORMALIZED truncated output. diff --git a/src/vllm/model_executor/models/minimax_h3_vision_gguf.cpp b/src/vllm/model_executor/models/minimax_h3_vision_gguf.cpp index d3bbd224..161f966d 100644 --- a/src/vllm/model_executor/models/minimax_h3_vision_gguf.cpp +++ b/src/vllm/model_executor/models/minimax_h3_vision_gguf.cpp @@ -45,8 +45,11 @@ multimodal::Qwen3VLVisionConfig MiniMaxH3EncoderVisionConfig() { cfg.in_channels = 3; // H3's encoder carries 3 REAL DeepStack mergers (visual.deepstack_merger_list.{0,1,2}), // UNLIKE the Qwen3.6-27B (empty). The WHICH-layers taps are not in the weights-only - // GGUF; these are inferred evenly-spaced over depth 27 and must be confirmed against - // the upstream vision_config for a bit-correct DeepStack inject (spec §8.8 residual). + // GGUF but are now CONFIRMED against the release config: MiniMax-H3's text_encoder is + // Qwen3-VL-32B-Instruct, whose `vision_config.deepstack_visual_indexes = [8, 16, 24]` + // (depth 27) — identical to the Qwen3-VL-MoE vision tower (vllm-omni + // `Qwen3VLMoeVisionConfig` default, and the public Qwen/Qwen3-VL-30B-A3B config.json). + // The #86 inference was correct (spec §8.8). cfg.deepstack_visual_indexes = {8, 16, 24}; cfg.norm_eps = 1e-6f; return cfg; diff --git a/tests/vllm/models/test_minimax_h3.cpp b/tests/vllm/models/test_minimax_h3.cpp index cf8f4a0c..708e8e8f 100644 --- a/tests/vllm/models/test_minimax_h3.cpp +++ b/tests/vllm/models/test_minimax_h3.cpp @@ -6408,6 +6408,37 @@ TEST_CASE("minimax_h3: the DEVICE keep-quant encoder matches the host f32 refere CHECK(err <= 2e-3); CHECK(mag > 1e-3); // the tower produced something, not zeros for (float v : got) REQUIRE(std::isfinite(v)); + + // DEEPSTACK: the surface #86 could not cover — the DEVICE forward now takes the + // visual position mask + per-tap blocks and injects them into the first N layers, + // exactly like the gated host reference and upstream `_deepstack_process`. Gate the + // device against the host reference WITH deepstack, and prove it changes the result. + std::vector visual_mask(static_cast(SEQ), 0); + visual_mask[1] = 1; + visual_mask[3] = 1; + visual_mask[4] = 1; + int64_t num_visual = 0; + for (uint8_t m : visual_mask) num_visual += m; + std::vector> deepstack; // one [num_visual, H] block per injected layer + for (int64_t l = 0; l < LAYERS; ++l) { + deepstack.push_back(MakeParam("encd.deepstack." + std::to_string(l), num_visual * H, 0.05)); + } + const std::vector want_deep = vllm::MiniMaxH3EncoderTextForward( + cfg, host, embeds, pos.data(), SEQ, visual_mask.data(), deepstack); + const std::vector got_deep = vllm::MiniMaxH3EncoderTextForwardDevice( + q, cfg, staged, embeds, pos.data(), SEQ, visual_mask.data(), deepstack); + REQUIRE(got_deep.size() == want_deep.size()); + double derr = 0.0, dmag = 0.0, delta = 0.0; + for (size_t i = 0; i < want_deep.size(); ++i) { + derr = std::max(derr, std::abs(static_cast(got_deep[i] - want_deep[i]))); + dmag = std::max(dmag, std::abs(static_cast(want_deep[i]))); + delta = std::max(delta, std::abs(static_cast(want_deep[i] - want[i]))); + } + INFO("device keep-quant encoder (deepstack) vs host: max|diff| = " << derr << " (scale " << dmag + << ")"); + CHECK(derr <= 2e-3); + CHECK(delta > 1e-4); // DeepStack must actually move the conditioning, or the gate is vacuous + for (float v : got_deep) REQUIRE(std::isfinite(v)); } TEST_CASE("minimax_h3: the embedding gather decodes ONLY the rows it needs, exactly") {