uboot-ueye01/drivers/ehci-ra.c at main · nicechao/uboot-ueye01 · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
/*
 * (C) Copyright 2009, Ying Yuan Huang <yy_huang@ralinktech.com>
 * This code is based on ehci freescale driver
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <version.h>
#include <usb.h>

#include <rt_mmap.h>

#include "ehci.h"
#include "ehci-core.h"

#define USB0_HOST_MODE 0x400

/*
 * enter power saving mode
 */
static void enter_power_saving(void)
{
	u32 val;

	val = RALINK_REG(RT2880_RSTCTRL_REG);    // toggle host & device RST bit
	val |= (RALINK_UHST_RST | RALINK_UDEV_RST);
	RALINK_REG(RT2880_RSTCTRL_REG) = val;

	mdelay(10);

	val = RALINK_REG(RT2880_CLKCFG1_REG);
#if defined(RT5350_ASIC_BOARD)
	val &= ~(RALINK_UPHY0_CLK_EN);
#else
	val &= ~(RALINK_UPHY0_CLK_EN | RALINK_UPHY1_CLK_EN);
#endif
	RALINK_REG(RT2880_CLKCFG1_REG) = val;

	mdelay(1);
}

/*
 * leave power saving mode
 */
static void leave_power_saving(void)
{
	u32 val;

	val = RALINK_REG(RT2880_CLKCFG1_REG);
#if defined(RT5350_ASIC_BOARD)
	val |= (RALINK_UPHY0_CLK_EN);
#else
	val |= (RALINK_UPHY0_CLK_EN | RALINK_UPHY1_CLK_EN);
#endif
	RALINK_REG(RT2880_CLKCFG1_REG) = val;

	mdelay(10);

	val = RALINK_REG(RT2880_SYSCFG1_REG);
	val |= USB0_HOST_MODE;
	RALINK_REG(RT2880_SYSCFG1_REG) = val;

	mdelay(1);

	val = RALINK_REG(RT2880_RSTCTRL_REG);    // toggle host & device RST bit
	val &= ~(RALINK_UHST_RST | RALINK_UDEV_RST);
	RALINK_REG(RT2880_RSTCTRL_REG) = val;

	mdelay(100);
}

/*
 * Create the appropriate control structures to manage
 * a new EHCI host controller.
 */
int ehci_hcd_init(void)
{
#if defined(RT3352_ASIC_BOARD) || defined(RT3883_ASIC_BOARD) || defined(RT5350_ASIC_BOARD) || \
    defined(MT7620_ASIC_BOARD) || defined(MT7628_ASIC_BOARD)
	printf("* ehci_hcd_init *\n");
	leave_power_saving();

	hccr = (struct ehci_hccr *)(0xb01c0000);
	hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));

	printf("%s USB EHCI host init, hccr %x, hcor %x, hc_length %d\n",
		RLT_MTK_VENDOR_NAME, (uint32_t)hccr, (uint32_t)hcor, (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
	return 0;
#else

	return -1;
#endif
}

/*
 * Destroy the appropriate control structures corresponding
 * the the EHCI host controller.
 */
int ehci_hcd_stop(void)
{
	enter_power_saving();

	return 0;
}