FPGA: remove 2023.0 cruft in anticipation of 2023.1 release (#1476)

This is a port of #1474

Author: yuguen

DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_template/src/fpga_template.cpp

@@ -32,33 +32,25 @@ int main() {
   bool passed = false;
 
   try {
-// This design is tested with 2023.0, but also accounts for a syntax change in
-// 2023.1
-#if __INTEL_CLANG_COMPILER >= 20230100
+
+    // Use compile-time macros to select either:
+    //  - the FPGA emulator device (CPU emulation of the FPGA)
+    //  - the FPGA device (a real FPGA)
+    //  - the simulator device
 #if FPGA_SIMULATOR
     auto selector = sycl::ext::intel::fpga_simulator_selector_v;
 #elif FPGA_HARDWARE
     auto selector = sycl::ext::intel::fpga_selector_v;
 #else  // #if FPGA_EMULATOR
     auto selector = sycl::ext::intel::fpga_emulator_selector_v;
 #endif
-#elif __INTEL_CLANG_COMPILER >= 20230000
-#if FPGA_SIMULATOR
-    auto selector = sycl::ext::intel::fpga_simulator_selector{};
-#elif FPGA_HARDWARE
-    auto selector = sycl::ext::intel::fpga_selector{};
-#else  // #if FPGA_EMULATOR
-    auto selector = sycl::ext::intel::fpga_emulator_selector{};
-#endif
-#else
-    assert(false) && "this design requires oneAPI 2023.0 or 2023.1!"
-#endif
 
     sycl::queue q(selector, fpga_tools::exception_handler,
                   sycl::property::queue::enable_profiling{});
 
     auto device = q.get_device();
 
+    // make sure the device supports USM host allocations
     if (!device.has(sycl::aspect::usm_host_allocations)) {
       std::cerr << "This design must either target a board that supports USM "
                    "Host/Shared allocations, or IP Component Authoring. "

DirectProgramming/C++SYCL_FPGA/Tutorials/Tools/experimental/platform_designer/README.md

@@ -179,7 +179,8 @@ Follow these steps to compile and test the design:
 
    ```
    > cd .. # navigate to project root if not there already
-   > xcopy add-oneapi\build\add.fpga_ip_export.prj_1\ add-quartus\add.fpga_ip_export.prj_1 /e /s /i
+   > ROBOCOPY add-oneapi\build\add.fpga_ip_export.prj_1\ add-quartus\add.fpga_ip_export.prj_1\ /S
+
    ```
 
 4. Create the Platform Designer system.