From b77f77b2af3b47b633961050bd42edfc92b40cf3 Mon Sep 17 00:00:00 2001 From: "Wang, Di5" Date: Mon, 13 Mar 2023 06:28:55 -0700 Subject: [PATCH 1/2] set fp-model to precise for emu only --- .../Tutorials/Features/ac_fixed/src/CMakeLists.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt index 9d7c4f182a..1f487340ef 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt @@ -20,16 +20,18 @@ endif() if(WIN32) set(WIN_FLAG "/EHsc") set(AC_TYPES_FLAG "/Qactypes") + set(EMULATOR_PLATFORM_FLAGS "/fp:precise") else() set(AC_TYPES_FLAG "-qactypes") + set(EMULATOR_PLATFORM_FLAGS "-fp-model=precise") endif() # A SYCL ahead-of-time (AoT) compile processes the device code in two stages. # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -DFPGA_EMULATOR -Wall ${WIN_FLAG}") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${EMULATOR_PLATFORM_FLAGS} ${AC_TYPES_FLAG} -DFPGA_EMULATOR -Wall ${WIN_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${EMULATOR_PLATFORM_FLAGS} ${AC_TYPES_FLAG}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -DFPGA_SIMULATOR -Wall ${WIN_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") set(REPORT_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Wall ${WIN_FLAG} -DFPGA_REPORT") From f61d32ec30458ab6832dc053bf3811f122c3269e Mon Sep 17 00:00:00 2001 From: "Wang, Di5" Date: Thu, 23 Mar 2023 13:57:04 -0700 Subject: [PATCH 2/2] set fp-model to precise for all platforms --- .../C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md | 2 ++ .../Tutorials/Features/ac_fixed/src/CMakeLists.txt | 10 ++++------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md index 92aec14561..23ed2b47d1 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/README.md @@ -132,6 +132,8 @@ When you use the `ac_fixed` library, keep the following points in mind: The host program for this tutorial shows the accuracy differences between the result provided by floating point math library and the result provided by the `ac_fixed` math library functions, where the `float` version generates a more accurate result than the smaller-sized `ac_fixed` version. + Note: the program is compiled with fp-model set to "precise", so the accuracy of the floating-point math functions conform to the IEEE standard. + - Emulation vs FPGA Hardware for fixed point math operations Due to the differences in the internal math implementations, the results from `ac_fixed` math functions in emulation and FPGA hardware might not always be bit-accurate. This tutorial shows how to build and run the sample for emulation and FPGA hardware so you can observe the difference. diff --git a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt index 1f487340ef..a1697f654d 100755 --- a/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt +++ b/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/ac_fixed/src/CMakeLists.txt @@ -19,19 +19,17 @@ endif() # 2. /Qactypes Include ac_types headers and link against ac_types emulation libraries if(WIN32) set(WIN_FLAG "/EHsc") - set(AC_TYPES_FLAG "/Qactypes") - set(EMULATOR_PLATFORM_FLAGS "/fp:precise") + set(AC_TYPES_FLAG "/Qactypes /fp:precise") else() - set(AC_TYPES_FLAG "-qactypes") - set(EMULATOR_PLATFORM_FLAGS "-fp-model=precise") + set(AC_TYPES_FLAG "-qactypes -fp-model=precise") endif() # A SYCL ahead-of-time (AoT) compile processes the device code in two stages. # 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V). # 2. The "link" stage invokes the compiler's FPGA backend before linking. # For this reason, FPGA backend flags must be passed as link flags in CMake. -set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${EMULATOR_PLATFORM_FLAGS} ${AC_TYPES_FLAG} -DFPGA_EMULATOR -Wall ${WIN_FLAG}") -set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${EMULATOR_PLATFORM_FLAGS} ${AC_TYPES_FLAG}") +set(EMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -DFPGA_EMULATOR -Wall ${WIN_FLAG}") +set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG}") set(SIMULATOR_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -DFPGA_SIMULATOR -Wall ${WIN_FLAG}") set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}") set(REPORT_COMPILE_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} -Wall ${WIN_FLAG} -DFPGA_REPORT")