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JIT compilation on ARM processors (openmm#3517)
* Upgraded to new version of asmjit * JIT compilation for ARM * Updated CMake script
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‎CMakeLists.txt‎

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@@ -247,8 +247,8 @@ IF(X86)
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ELSE()
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SET_SOURCE_FILES_PROPERTIES(${CMAKE_SOURCE_DIR}/libraries/sfmt/src/SFMT.cpp PROPERTIES COMPILE_FLAGS "-UHAVE_SSE2")
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ENDIF()
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IF(X86 AND NOT (WIN32 AND OPENMM_BUILD_STATIC_LIB))
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FILE(GLOB src_files ${CMAKE_CURRENT_SOURCE_DIR}/libraries/asmjit/*/*.cpp)
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IF((X86 OR ARM) AND NOT (WIN32 AND OPENMM_BUILD_STATIC_LIB))
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FILE(GLOB src_files ${CMAKE_CURRENT_SOURCE_DIR}/libraries/asmjit/asmjit/*/*.cpp)
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FILE(GLOB incl_files ${CMAKE_CURRENT_SOURCE_DIR}/libraries/asmjit/*.h)
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SET(SOURCE_FILES ${SOURCE_FILES} ${src_files})
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SET(SOURCE_INCLUDE_FILES ${SOURCE_INCLUDE_FILES} ${incl_files})

‎libraries/asmjit/arm.h‎

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This file was deleted.

‎libraries/asmjit/asmjit.h‎

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This file was deleted.

libraries/asmjit/LICENSE.md renamed to libraries/asmjit/asmjit/LICENSE.md

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Copyright (c) 2008-2017, Petr Kobalicek
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Copyright (c) 2008-2020 The AsmJit Authors
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This software is provided 'as-is', without any express or implied
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warranty. In no event will the authors be held liable for any damages

‎libraries/asmjit/asmjit/a64.h‎

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// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#ifndef ASMJIT_A64_H_INCLUDED
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#define ASMJIT_A64_H_INCLUDED
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//! \addtogroup asmjit_a64
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//!
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//! ### Emitters
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//!
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//! - \ref a64::Assembler - AArch64 assembler (must read, provides examples).
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//! - \ref a64::Builder - AArch64 builder.
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//! - \ref a64::Compiler - AArch64 compiler.
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//! - \ref a64::Emitter - AArch64 emitter (abstract).
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//!
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//! ### Supported Instructions
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//!
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//! - Emitters:
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//! - \ref a64::EmitterExplicitT - Provides all instructions that use explicit
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//! operands, provides also utility functions. The member functions provided
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//! are part of all ARM/AArch64 emitters.
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//!
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//! - Instruction representation:
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//! - \ref a64::Inst::Id - instruction identifiers.
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//!
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//! ### Register Operands
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//!
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//! - \ref arm::Reg - Base class for any AArch32/AArch64 register.
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//! - \ref arm::Gp - General purpose register:
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//! - \ref arm::GpW - 32-bit register.
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//! - \ref arm::GpX - 64-bit register.
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//! - \ref arm::Vec - Vector (SIMD) register:
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//! - \ref arm::VecB - 8-bit SIMD register (AArch64 only).
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//! - \ref arm::VecH - 16-bit SIMD register (AArch64 only).
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//! - \ref arm::VecS - 32-bit SIMD register.
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//! - \ref arm::VecD - 64-bit SIMD register.
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//! - \ref arm::VecV - 128-bit SIMD register.
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//!
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//! ### Memory Operands
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//!
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//! - \ref arm::Mem - AArch32/AArch64 memory operand that provides support for all ARM addressing features
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//! including base, index, pre/post increment, and ARM-specific shift addressing and index extending.
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//!
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//! ### Other
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//!
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//! - \ref arm::Shift - Shift operation and value.
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//! - \ref a64::Utils - Utilities that can help during code generation for AArch64.
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#include "./arm.h"
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#include "./arm/a64assembler.h"
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#include "./arm/a64builder.h"
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#include "./arm/a64compiler.h"
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#include "./arm/a64emitter.h"
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#include "./arm/a64globals.h"
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#include "./arm/a64instdb.h"
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#include "./arm/a64operand.h"
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#include "./arm/a64utils.h"
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#endif // ASMJIT_A64_H_INCLUDED
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‎libraries/asmjit/asmjit/arm.h‎

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// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#ifndef ASMJIT_ARM_H_INCLUDED
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#define ASMJIT_ARM_H_INCLUDED
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//! \addtogroup asmjit_arm
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//!
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//! ### Namespaces
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//!
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//! - \ref arm - arm namespace provides common functionality for both AArch32 and AArch64 backends.
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//! - \ref a64 - a64 namespace provides support for AArch64 architecture. In addition it includes
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//! \ref arm namespace, so you can only use a single namespace when targeting AArch64 architecture.
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//!
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//! ### Emitters
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//!
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//! - AArch64
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//! - \ref a64::Assembler - AArch64 assembler (must read, provides examples).
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//! - \ref a64::Builder - AArch64 builder.
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//! - \ref a64::Compiler - AArch64 compiler.
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//! - \ref a64::Emitter - AArch64 emitter (abstract).
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//!
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//! ### Supported Instructions
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//!
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//! - AArch64:
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//! - Emitters:
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//! - \ref a64::EmitterExplicitT - Provides all instructions that use explicit operands, provides also
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//! utility functions. The member functions provided are part of all AArch64 emitters.
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//! - Instruction representation:
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//! - \ref a64::Inst::Id - instruction identifiers.
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//!
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//! ### Register Operands
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//!
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//! - \ref arm::Reg - Base class for any AArch32/AArch64 register.
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//! - \ref arm::Gp - General purpose register:
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//! - \ref arm::GpW - 32-bit register.
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//! - \ref arm::GpX - 64-bit register.
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//! - \ref arm::Vec - Vector (SIMD) register:
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//! - \ref arm::VecB - 8-bit SIMD register (AArch64 only).
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//! - \ref arm::VecH - 16-bit SIMD register (AArch64 only).
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//! - \ref arm::VecS - 32-bit SIMD register.
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//! - \ref arm::VecD - 64-bit SIMD register.
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//! - \ref arm::VecV - 128-bit SIMD register.
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//!
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//! ### Memory Operands
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//!
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//! - \ref arm::Mem - AArch32/AArch64 memory operand that provides support for all ARM addressing features
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//! including base, index, pre/post increment, and ARM-specific shift addressing and index extending.
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//!
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//! ### Other
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//!
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//! - \ref arm::Shift - Shift operation and value (both AArch32 and AArch64).
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//! - \ref arm::DataType - Data type that is part of an instruction in AArch32 mode.
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//! - \ref a64::Utils - Utilities that can help during code generation for AArch64.
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#include "./core.h"
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#include "./arm/armglobals.h"
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#include "./arm/armoperand.h"
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#endif // ASMJIT_ARM_H_INCLUDED

‎libraries/asmjit/asmjit/arm/a64archtraits_p.h‎

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// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#ifndef ASMJIT_ARM_A64ARCHTRAITS_P_H_INCLUDED
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#define ASMJIT_ARM_A64ARCHTRAITS_P_H_INCLUDED
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#include "../core/archtraits.h"
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#include "../core/misc_p.h"
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#include "../core/type.h"
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#include "../arm/a64operand.h"
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ASMJIT_BEGIN_SUB_NAMESPACE(a64)
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//! \cond INTERNAL
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//! \addtogroup asmjit_a64
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//! \{
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static const constexpr ArchTraits a64ArchTraits = {
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// SP/FP/LR/PC.
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Gp::kIdSp, Gp::kIdFp, Gp::kIdLr, 0xFF,
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// Reserved.
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{ 0, 0, 0 },
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// HW stack alignment (AArch64 requires stack aligned to 64 bytes).
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16,
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// Min/max stack offset - byte addressing is the worst, VecQ addressing the best.
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4095, 65520,
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// Instruction hints [Gp, Vec, ExtraVirt2, ExtraVirt3].
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{{
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InstHints::kPushPop,
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InstHints::kPushPop,
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InstHints::kNoHints,
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InstHints::kNoHints
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}},
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// RegInfo.
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#define V(index) OperandSignature{arm::RegTraits<RegType(index)>::kSignature}
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{{ ASMJIT_LOOKUP_TABLE_32(V, 0) }},
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#undef V
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// RegTypeToTypeId.
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#define V(index) TypeId(arm::RegTraits<RegType(index)>::kTypeId)
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{{ ASMJIT_LOOKUP_TABLE_32(V, 0) }},
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#undef V
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// TypeIdToRegType.
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#define V(index) (index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kInt8) ? RegType::kARM_GpW : \
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index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kUInt8) ? RegType::kARM_GpW : \
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index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kInt16) ? RegType::kARM_GpW : \
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index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kUInt16) ? RegType::kARM_GpW : \
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index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kInt32) ? RegType::kARM_GpW : \
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index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kUInt32) ? RegType::kARM_GpW : \
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index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kInt64) ? RegType::kARM_GpX : \
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index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kUInt64) ? RegType::kARM_GpX : \
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index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kIntPtr) ? RegType::kARM_GpX : \
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index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kUIntPtr) ? RegType::kARM_GpX : \
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index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kFloat32) ? RegType::kARM_VecS : \
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index + uint32_t(TypeId::_kBaseStart) == uint32_t(TypeId::kFloat64) ? RegType::kARM_VecD : RegType::kNone)
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{{ ASMJIT_LOOKUP_TABLE_32(V, 0) }},
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#undef V
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// Word names of 8-bit, 16-bit, 32-bit, and 64-bit quantities.
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{
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ArchTypeNameId::kByte,
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ArchTypeNameId::kHWord,
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ArchTypeNameId::kWord,
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ArchTypeNameId::kXWord
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}
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};
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//! \}
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//! \endcond
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ASMJIT_END_SUB_NAMESPACE
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#endif // ASMJIT_ARM_A64ARCHTRAITS_P_H_INCLUDED

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