From 29f3c2a6e2472a3030cd6a2ac10fb9716d3f768e Mon Sep 17 00:00:00 2001 From: Arnaud Le Blanc Date: Mon, 20 Jul 2026 16:57:18 +0200 Subject: [PATCH 1/2] zend_jit_resolve_tsrm_ls_cache_offsets: clobber volatile registers --- ext/opcache/jit/tls/zend_jit_tls_aarch64.c | 11 ++++++++++- ext/opcache/jit/tls/zend_jit_tls_x86.c | 6 ++++++ ext/opcache/jit/tls/zend_jit_tls_x86_64.c | 7 +++++++ 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/ext/opcache/jit/tls/zend_jit_tls_aarch64.c b/ext/opcache/jit/tls/zend_jit_tls_aarch64.c index 24f0f88454b6..1a036ca4a806 100644 --- a/ext/opcache/jit/tls/zend_jit_tls_aarch64.c +++ b/ext/opcache/jit/tls/zend_jit_tls_aarch64.c @@ -126,7 +126,16 @@ zend_result zend_jit_resolve_tsrm_ls_cache_offsets( "add %2, x8, x0\n" : "=r" (thread_pointer), "=r" (insn), "=r" (addr) : - : "x0", "x1", "x8"); + /* call may clobber volatile registers */ + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17", "x18", "x30", + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", + "cc", "memory" + ); ZEND_ASSERT(addr == &_tsrm_ls_cache); diff --git a/ext/opcache/jit/tls/zend_jit_tls_x86.c b/ext/opcache/jit/tls/zend_jit_tls_x86.c index 4e06bbd1eacd..04ab195b708a 100644 --- a/ext/opcache/jit/tls/zend_jit_tls_x86.c +++ b/ext/opcache/jit/tls/zend_jit_tls_x86.c @@ -110,6 +110,12 @@ zend_result zend_jit_resolve_tsrm_ls_cache_offsets( /* Load thread pointer address */ "movl %%gs:0, %%ebx\n" : "=a" (t_addr), "=S" (code), "=b" (thread_pointer) + : + /* call may clobber volatile registers */ + : "ecx", "edx", + "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", + "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", + "cc", "memory" ); ZEND_ASSERT(t_addr == &_tsrm_ls_cache); diff --git a/ext/opcache/jit/tls/zend_jit_tls_x86_64.c b/ext/opcache/jit/tls/zend_jit_tls_x86_64.c index 11ffe495fcbb..f177509ba554 100644 --- a/ext/opcache/jit/tls/zend_jit_tls_x86_64.c +++ b/ext/opcache/jit/tls/zend_jit_tls_x86_64.c @@ -106,6 +106,13 @@ zend_result zend_jit_resolve_tsrm_ls_cache_offsets( /* Load thread pointer address */ "movq %%fs:0, %%rsi\n" : "=a" (addr), "=b" (code), "=S" (thread_pointer) + : + /* call may clobber volatile registers */ + : "rcx", "rdx", "rdi", + "r8", "r9", "r10", "r11", + "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", + "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", + "cc", "memory" ); ZEND_ASSERT(addr == &_tsrm_ls_cache); From b67da92ea95686a6270331f8f04d0319aa9a33e0 Mon Sep 17 00:00:00 2001 From: Arnaud Le Blanc Date: Tue, 21 Jul 2026 09:17:59 +0200 Subject: [PATCH 2/2] Update clobber lists --- ext/opcache/jit/tls/zend_jit_tls_aarch64.c | 13 +++---------- ext/opcache/jit/tls/zend_jit_tls_x86_64.c | 1 + 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/ext/opcache/jit/tls/zend_jit_tls_aarch64.c b/ext/opcache/jit/tls/zend_jit_tls_aarch64.c index 1a036ca4a806..43be504aeff9 100644 --- a/ext/opcache/jit/tls/zend_jit_tls_aarch64.c +++ b/ext/opcache/jit/tls/zend_jit_tls_aarch64.c @@ -126,16 +126,9 @@ zend_result zend_jit_resolve_tsrm_ls_cache_offsets( "add %2, x8, x0\n" : "=r" (thread_pointer), "=r" (insn), "=r" (addr) : - /* call may clobber volatile registers */ - : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", - "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", - "x16", "x17", "x18", "x30", - "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", - "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", - "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", - "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", - "cc", "memory" - ); + /* Resolver call clobbers only a few registers: https://github.com/ARM-software/abi-aa/blob/ee4b3c12d57c8424ff60c2ae56e10690d0604ab6/sysvabi64/sysvabi64.rst#calling-convention. + * We also clobber x8. */ + : "x0", "x1", "x8", "x30", "cc", "memory"); ZEND_ASSERT(addr == &_tsrm_ls_cache); diff --git a/ext/opcache/jit/tls/zend_jit_tls_x86_64.c b/ext/opcache/jit/tls/zend_jit_tls_x86_64.c index f177509ba554..620056a70664 100644 --- a/ext/opcache/jit/tls/zend_jit_tls_x86_64.c +++ b/ext/opcache/jit/tls/zend_jit_tls_x86_64.c @@ -110,6 +110,7 @@ zend_result zend_jit_resolve_tsrm_ls_cache_offsets( /* call may clobber volatile registers */ : "rcx", "rdx", "rdi", "r8", "r9", "r10", "r11", + "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "cc", "memory"