Add support for generating VCD files from testbenches

    Add generation of Value Change Dump (VCD) files from the
    testbenches. This allow the use of waveform viewers to look at
    registers, signals etc during simulation. The patch also adds the
    ability to remove vcd file when doing 'make clean'.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>

Author: secworks

src/tb/tb_aes.v

@@ -549,6 +549,10 @@ module tb_aes();
       $display("    ==============================");
       $display("");
 
+      $display("Dumping all variables to tb_aes vcd file.");
+      $dumpfile("tb_aes.vcd");
+      $dumpvars(0, tb_aes);
+
       init_sim();
       dump_dut_state();
       reset_dut();
@@ -559,7 +563,9 @@ module tb_aes();
       display_test_results();
 
       $display("");
-      $display("*** AES simulation done. ***");
+      $display("   -= Testbench for AES completed =-");
+      $display("    ===============================");
+      $display("");
       $finish;
     end // main
 endmodule // tb_aes

src/tb/tb_aes_core.v

@@ -404,6 +404,10 @@ module tb_aes_core();
       $display("     ================================");
       $display("");
 
+      $display("tb: Dumping all variables to tb_aes_core vcd file.");
+      $dumpfile("tb_aes_core.vcd");
+      $dumpvars(0, tb_aes_core);
+
       init_sim();
       dump_dut_state();
       reset_dut();
@@ -482,7 +486,10 @@ module tb_aes_core();
 
       display_test_result();
       $display("");
-      $display("*** AES core simulation done. ***");
+
+      $display("   -= Testbench for aes core cmpleted =-");
+      $display("     =================================");
+      $display("");
       $finish;
     end // aes_core_test
 endmodule // tb_aes_core

src/tb/tb_aes_decipher_block.v

@@ -340,6 +340,10 @@ module tb_aes_decipher_block();
       $display("     ============================================");
       $display("");
 
+      $display("Dumping all variables to tb_aes_decipher_block vcd file.");
+      $dumpfile("tb_aes_decipher_block.vcd");
+      $dumpvars(0, tb_aes_decipher_block);
+
       init_sim();
       dump_dut_state();
       reset_dut();
@@ -394,7 +398,9 @@ module tb_aes_decipher_block();
 
       display_test_result();
       $display("");
-      $display("*** AES decipher block module simulation done. ***");
+      $display("   -= Testbench for aes decipher block completed =-");
+      $display("     ============================================");
+      $display("");
       $finish;
     end // aes_core_test
 endmodule // tb_aes_decipher_block

src/tb/tb_aes_encipher_block.v

@@ -534,6 +534,10 @@ module tb_aes_encipher_block();
       $display("     ============================================");
       $display("");
 
+      $display("Dumping all variables to tb_aes_encipher_block vcd file.");
+      $dumpfile("tb_aes_encipher_block.vcd");
+      $dumpvars(0, tb_aes_encipher_block);
+
       init_sim();
       reset_dut();
 

src/tb/tb_aes_key_mem.v

@@ -428,6 +428,10 @@ module tb_aes_key_mem();
       $display("    =====================================");
       $display("");
 
+      $display("Dumping all variables to tb_aes_key_mem vcd file.");
+      $dumpfile("tb_aes_key_mem.vcd");
+      $dumpvars(0, tb_aes_key_mem);
+
       init_sim();
       dump_dut_state();
       reset_dut();
@@ -639,8 +643,10 @@ module tb_aes_key_mem();
 
 
       display_test_result();
+
       $display("");
-      $display("*** AES core simulation done. ***");
+      $display("   -= Testbench for aes key mem completed =-");
+      $display("    =======================================");
       $finish;
     end // aes_key_mem_test
 endmodule // tb_aes_key_mem

toolruns/Makefile

@@ -109,7 +109,7 @@ clean:
 	rm -f keymem.sim
 	rm -f core.sim
 	rm -f top.sim
-
+	rm -f *.vcd
 
 help:
 	@echo "Build system for simulation of AES Verilog core"