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286 | 286 | #define FEAT_HAS_SOFTREND BUILD_COMPILER == COMPILER_VC //GCC wants us to enable sse4 globaly to enable intrins |
287 | 287 | #endif |
288 | 288 |
|
289 | | -#define RAM_SIZE_MAX (32*1024*1024) |
290 | | -#define VRAM_SIZE_MAX (16*1024*1024) |
291 | | -#define ARAM_SIZE_MAX (8*1024*1024) |
292 | | - |
293 | 289 | //Depricated build configs |
294 | 290 | #ifdef HOST_NO_REC |
295 | 291 | #error Dont use HOST_NO_REC |
|
298 | 294 | #ifdef HOST_NO_AREC |
299 | 295 | #error Dont use HOST_NO_AREC |
300 | 296 | #endif |
| 297 | + |
| 298 | +// TARGET PLATFORM |
| 299 | + |
| 300 | +#define RAM_SIZE_MAX (32*1024*1024) |
| 301 | +#define VRAM_SIZE_MAX (16*1024*1024) |
| 302 | +#define ARAM_SIZE_MAX (8*1024*1024) |
| 303 | + |
| 304 | +#if (DC_PLATFORM==DC_PLATFORM_DREAMCAST) |
| 305 | + |
| 306 | + #define BUILD_DREAMCAST 1 |
| 307 | + |
| 308 | + //DC : 16 mb ram, 8 mb vram, 2 mb aram, 2 mb bios, 128k flash |
| 309 | + #define RAM_SIZE (16*1024*1024) |
| 310 | + #define VRAM_SIZE (8*1024*1024) |
| 311 | + #define ARAM_SIZE (2*1024*1024) |
| 312 | + #define BIOS_SIZE (2*1024*1024) |
| 313 | + #define FLASH_SIZE (128*1024) |
| 314 | + |
| 315 | + #define ROM_PREFIX "dc_" |
| 316 | + #define ROM_NAMES |
| 317 | + #define NVR_OPTIONAL 0 |
| 318 | + |
| 319 | +#elif (DC_PLATFORM==DC_PLATFORM_DEV_UNIT) |
| 320 | + |
| 321 | + #define BUILD_DEV_UNIT 1 |
| 322 | + |
| 323 | + //Devkit : 32 mb ram, 8? mb vram, 2? mb aram, 2? mb bios, ? flash |
| 324 | + #define RAM_SIZE (32*1024*1024) |
| 325 | + #define VRAM_SIZE (8*1024*1024) |
| 326 | + #define ARAM_SIZE (2*1024*1024) |
| 327 | + #define BIOS_SIZE (2*1024*1024) |
| 328 | + #define FLASH_SIZE (128*1024) |
| 329 | + |
| 330 | + #define ROM_PREFIX "hkt_" |
| 331 | + #define ROM_NAMES |
| 332 | + #define NVR_OPTIONAL 0 |
| 333 | + |
| 334 | +#elif (DC_PLATFORM==DC_PLATFORM_NAOMI) |
| 335 | + |
| 336 | + //Naomi : 32 mb ram, 16 mb vram, 8 mb aram, 2 mb bios, ? flash |
| 337 | + #define RAM_SIZE (32*1024*1024) |
| 338 | + #define VRAM_SIZE (16*1024*1024) |
| 339 | + #define ARAM_SIZE (8*1024*1024) |
| 340 | + #define BIOS_SIZE (2*1024*1024) |
| 341 | + #define BBSRAM_SIZE (32*1024) |
| 342 | + |
| 343 | + #define ROM_PREFIX "naomi_" |
| 344 | + #define ROM_NAMES ";epr-21576d.bin" |
| 345 | + #define NVR_OPTIONAL 1 |
| 346 | + |
| 347 | +#elif (DC_PLATFORM==DC_PLATFORM_NAOMI2) |
| 348 | + |
| 349 | + //Naomi2 : 32 mb ram, 16 mb vram, 8 mb aram, 2 mb bios, ? flash |
| 350 | + #define RAM_SIZE (32*1024*1024) |
| 351 | + #define VRAM_SIZE (16*1024*1024) |
| 352 | + #define ARAM_SIZE (8*1024*1024) |
| 353 | + #define BIOS_SIZE (2*1024*1024) |
| 354 | + #define BBSRAM_SIZE (32*1024) |
| 355 | + |
| 356 | + #define ROM_PREFIX "n2_" |
| 357 | + #define ROM_NAMES |
| 358 | + #define NVR_OPTIONAL 1 |
| 359 | + |
| 360 | +#elif (DC_PLATFORM==DC_PLATFORM_ATOMISWAVE) |
| 361 | + |
| 362 | + #define BUILD_ATOMISWAVE 1 |
| 363 | + |
| 364 | + //Atomiswave : 16 mb ram, 8 mb vram, 8 mb aram, 128kb bios on flash, 128kb battery-backed ram |
| 365 | + #define RAM_SIZE (16*1024*1024) |
| 366 | + #define VRAM_SIZE (8*1024*1024) |
| 367 | + #define ARAM_SIZE (8*1024*1024) |
| 368 | + #define BIOS_SIZE (128*1024) |
| 369 | + #define BBSRAM_SIZE (128*1024) |
| 370 | + |
| 371 | + #define ROM_PREFIX "aw_" |
| 372 | + #define ROM_NAMES ";bios.ic23_l" |
| 373 | + #define NVR_OPTIONAL 1 |
| 374 | + |
| 375 | +#else |
| 376 | + #error invalid build config |
| 377 | +#endif |
| 378 | + |
| 379 | +#define RAM_MASK (RAM_SIZE-1) |
| 380 | +#define VRAM_MASK (VRAM_SIZE-1) |
| 381 | +#define ARAM_MASK (ARAM_SIZE-1) |
| 382 | +#define BIOS_MASK (BIOS_SIZE-1) |
| 383 | + |
| 384 | +#ifdef FLASH_SIZE |
| 385 | +#define FLASH_MASK (FLASH_SIZE-1) |
| 386 | +#endif |
| 387 | + |
| 388 | +#ifdef BBSRAM_SIZE |
| 389 | +#define BBSRAM_MASK (BBSRAM_SIZE-1) |
| 390 | +#endif |
| 391 | + |
| 392 | +#define GD_CLOCK 33868800 //GDROM XTAL -- 768fs |
| 393 | + |
| 394 | +#define AICA_CORE_CLOCK (GD_CLOCK*4/3) //[45158400] GD->PLL 3:4 -> AICA CORE -- 1024fs |
| 395 | +#define ADAC_CLOCK (AICA_CORE_CLOCK/2) //[11289600] 44100*256, AICA CORE -> PLL 4:1 -> ADAC -- 256fs |
| 396 | +#define AICA_ARM_CLOCK (AICA_CORE_CLOCK/2) //[22579200] AICA CORE -> PLL 2:1 -> ARM |
| 397 | +#define AICA_SDRAM_CLOCK (GD_CLOCK*2) //[67737600] GD-> PLL 2 -> SDRAM |
| 398 | +#define SH4_MAIN_CLOCK (200*1000*1000) //[200000000] XTal(13.5) -> PLL (33.3) -> PLL 1:6 (200) |
| 399 | +#define SH4_RAM_CLOCK (100*1000*1000) //[100000000] XTal(13.5) -> PLL (33.3) -> PLL 1:3 (100) , also suplied to HOLLY chip |
| 400 | +#define G2_BUS_CLOCK (25*1000*1000) //[25000000] from Holly, from SH4_RAM_CLOCK w/ 2 2:1 plls |
| 401 | + |
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