@@ -229,9 +229,6 @@ class Arm64Assembler : public MacroAssembler
229229 typedef void (MacroAssembler::*Arm64Op_RROF)(const Register&, const Register&, const Operand&, enum FlagsUpdate);
230230
231231public:
232- Arm64Assembler () : Arm64Assembler(emit_GetCCPtr())
233- {
234- }
235232 Arm64Assembler (void *buffer) : MacroAssembler((u8 *)buffer, 64 * 1024 ), regalloc(this )
236233 {
237234 call_regs.push_back (&w0);
@@ -1148,15 +1145,13 @@ class Arm64Assembler : public MacroAssembler
11481145 if (!_nvmem_enabled ())
11491146 return false ;
11501147
1151- Instruction *start_instruction = GetCursorAddress<Instruction *>();
1152-
11531148 // WARNING: the rewrite code relies on having two ops before the memory access
11541149 // Update ngen_Rewrite (and perhaps read_memory_rewrite_size) if adding or removing code
1150+ Instruction *start_instruction = GetCursorAddress<Instruction *>();
11551151 Add (w1, *call_regs[0 ], sizeof (Sh4Context), LeaveFlags);
11561152 Bfc (w1, 29 , 3 ); // addr &= ~0xE0000000
1157-
1158- // printf("direct read memory access opid %d pc %p code addr %08x\n", opid, GetCursorAddress<void *>(), this->block->addr);
1159- this ->block ->memory_accesses [GetCursorAddress<void *>()] = (u32 )opid;
1153+ Instruction *mem_instruction = GetCursorAddress<Instruction *>();
1154+ unsigned prologue_size = (char *)mem_instruction - (char *)start_instruction;
11601155
11611156 u32 size = op.flags & 0x7f ;
11621157 switch (size)
@@ -1192,7 +1187,10 @@ class Arm64Assembler : public MacroAssembler
11921187 Str (x1, sh4_context_mem_operand (op.rd .reg_ptr ()));
11931188#endif
11941189 }
1190+ unsigned code_size = (unsigned )(GetCursorAddress<char *>() - (char *)start_instruction);
11951191 EnsureCodeSize (start_instruction, read_memory_rewrite_size);
1192+ verify (code_size < 256 && prologue_size < 256 );
1193+ this ->block ->memory_accesses [mem_instruction] = { (uint16_t )opid, (uint8_t )prologue_size, (uint8_t )code_size };
11961194
11971195 return true ;
11981196 }
@@ -1228,15 +1226,13 @@ class Arm64Assembler : public MacroAssembler
12281226 if (!_nvmem_enabled ())
12291227 return false ;
12301228
1231- Instruction *start_instruction = GetCursorAddress<Instruction *>();
1232-
12331229 // WARNING: the rewrite code relies on having two ops before the memory access
12341230 // Update ngen_Rewrite (and perhaps write_memory_rewrite_size) if adding or removing code
1231+ Instruction *start_instruction = GetCursorAddress<Instruction *>();
12351232 Add (w7, *call_regs[0 ], sizeof (Sh4Context), LeaveFlags);
12361233 Bfc (w7, 29 , 3 ); // addr &= ~0xE0000000
1237-
1238- // printf("direct write memory access opid %d pc %p code addr %08x\n", opid, GetCursorAddress<void *>(), this->block->addr);
1239- this ->block ->memory_accesses [GetCursorAddress<void *>()] = (u32 )opid;
1234+ Instruction *mem_instruction = GetCursorAddress<Instruction *>();
1235+ unsigned prologue_size = (char *)mem_instruction - (char *)start_instruction;
12401236
12411237 u32 size = op.flags & 0x7f ;
12421238 switch (size)
@@ -1257,7 +1253,11 @@ class Arm64Assembler : public MacroAssembler
12571253 Str (x1, MemOperand (x28, x7));
12581254 break ;
12591255 }
1256+
1257+ unsigned code_size = (unsigned )(GetCursorAddress<char *>() - (char *)start_instruction);
12601258 EnsureCodeSize (start_instruction, write_memory_rewrite_size);
1259+ verify (code_size < 256 && prologue_size < 256 );
1260+ this ->block ->memory_accesses [mem_instruction] = { (uint16_t )opid, (uint8_t )prologue_size, (uint8_t )code_size };
12611261
12621262 return true ;
12631263 }
@@ -1411,7 +1411,7 @@ void ngen_Compile(RuntimeBlockInfo* block, SmcCheckEnum smc_checks, bool reset,
14111411{
14121412 verify (emit_FreeSpace () >= 16 * 1024 );
14131413
1414- compiler = new Arm64Assembler ();
1414+ compiler = new Arm64Assembler (emit_GetCCPtr () );
14151415
14161416 compiler->ngen_Compile (block, smc_checks, reset, staging, optimise);
14171417
@@ -1456,7 +1456,7 @@ bool ngen_Rewrite(unat& host_pc, unat, unat)
14561456 printf (" ngen_Rewrite: memory access at %p not found (%lu entries)\n " , code_ptr, block->memory_accesses .size ());
14571457 return false ;
14581458 }
1459- u32 opid = it->second ;
1459+ u32 opid = it->second . opid ;
14601460 verify (opid < block->oplist .size ());
14611461 const shil_opcode& op = block->oplist [opid];
14621462 Arm64Assembler *assembler = new Arm64Assembler (code_ptr - 2 ); // Skip the 2 preceding ops (bic, add)
0 commit comments