Added uart_sum example (Add two 8-bit numbers on FPGA and return result via UART) (#23)

* Added uart_sum example

Author: dayshaun-1

examples/uart_sum/README.md

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+# Add Two 8-bit Numbers on FPGA and Return Result via UART
+This project demonstrates UART-based communication between an RP2040 and an FPGA. Two 8-bit numbers are sent from the RP2040 to the FPGA over UART. The FPGA stores the received values, performs an addition operation, and then transmits the result back to the RP2040 using UART.
+
+## Overview on FPGA side
+- This project consists of three modules :   
+    1) `top :` This module implements the FSM.
+        - Continuously look for input data
+        - Add the two 8 bit numbers.
+        - Generate appropriate transmission signal onces summation is done.
+    2) `uart_rx : ` This module implements a UART Receiver.
+        - When the data is received, it makes "data valid" signal high.
+    3) `uart_rx : ` This module implements a UART Transmitter.
+        - When the start signal is given, it transmit the data present in its output buffer.
+
+---
+
+## Features
+- Configurable `BAUD_RATE` 
+
+---
+
+## Top Module Interface
+
+| Signal        | Direction | Description                          |
+|---------------|-----|--------------------------------------|
+| `clk`         | In  | System clock (50 MHz typical)        |
+| `rst`        | In  | Reset Pin   |
+| `rx`        | In | Receiver Line |
+| `tx`  | Out | Transmission Line              |
+| `tx_en`     | Out | Output enable for transmitter (always 1)              |
+| `clk_en`      | Out | Clock enable (always 1)              |
+
+---
+
+## Parameters Used
+#### `CLK :` 
+- Parameter to represent the System clock frequency in Hz.
+    -  `parameter CLK = 50_000_000`
+#### `BAUD_RATE :` 
+- Parameter to configure Baud Rate of UART communication.
+     - `parameter BAUD_RATE = 115200`
+
+---
+
+## Pin Usage for Testing
+This design was tested using configuration given below:
+
+### FPGA 
+| FPGA GPIO Pin | Signal Name | Direction | Description                       |
+|----------|-------------|-----------|-----------------------------------|
+| 3       | Reset     | Input    | For Reseting the FPGA     |
+| 4       | UART TX     | Input     | UART ouput to RP2040    |
+| 6       | UART RX     | Output    | UART input from RP2040    |
+
+### RP2040
+| RP2040 Pin | Signal Name | Direction | Description                       |
+|----------|-------------|-----------|-----------------------------------|
+| 1       | UART RX     | Input     | UART input from FPGA    |
+| 0       | UART TX     | Output    | UART ouput to FPGA    |
+| 2       | Reset     | Output    | MCU output for reseting the FPGA     |
+
+When testing using RP2040 MCU, first load the bitstream to FPGA then run the `uart_sum.py`. The pin number in your FPGA constraints must match what is used in the micropython code.
+
+---
+
+## Expected Output in Thonny
+![Expected Output in Thonny](ffpga/images/output.JPG "Expected Output")

examples/uart_sum/ffpga/images/output.JPG

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+(* top *) module top #(
+       parameter CLK = 50_000_000,
+       parameter BAUD_RATE = 115200
+    )( 
+	  (* iopad_external_pin, clkbuf_inhibit *)input      clk,
+ 	  (* iopad_external_pin *) output     clk_en,
+	  (* iopad_external_pin *) input      rst,
+	  (* iopad_external_pin *) input      rx,
+	  (* iopad_external_pin *) output     tx,
+	  (* iopad_external_pin *) output     tx_en 
+);
+
+  assign clk_en = 1'b1;
+  assign tx_en = 1'b1;
+  
+  reg [7:0] num1, num2, sum;
+  reg flag = 1'b0;
+  
+ /* uart_rx module instantiation */
+  wire [7:0] data;
+  wire data_valid;
+  uart_rx # ( .CLK(CLK),
+  			 .BAUD_RATE(BAUD_RATE) ) 
+  U_uart_rx
+
+    ( 
+    .i_Clock(clk),
+    .i_RX_Serial(rx),
+    .o_RX_DV(data_valid),
+    .o_RX_Byte (data)
+    );
+    
+ /* uart_tx module instantiation */
+  uart_tx # ( .IN_CLK_HZ(CLK), 
+  			  .DATA_FRAME(8),          
+  			  .BAUD_RATE(BAUD_RATE),    
+  			  .OVERSAMPLING_MODE(16),        
+  			  .STOP_BIT(1),          
+  			  .LSB(1'b0) ) 
+  U_uart_tx
+  	(
+	.i_clk(clk),
+  	.i_rst(rst),
+  	.o_tx(tx),
+  	.i_tx_data(sum),    // sum = num1 + num2
+  	.i_tx_start(flag),  // transmit sum when flag is HIGH
+  	.o_tx_done() 
+	);
+
+  localparam S1  = 2'b00;
+  localparam S2  = 2'b01;
+  localparam S3  = 2'b10;
+  localparam S4  = 2'b11;
+	
+  reg [1:0] state = S1;	
+  always @(posedge clk) begin
+  	 if (rst) begin
+  	 	state <= S1;
+  	 end else begin
+  	 	if (state == S1 && data_valid) begin
+  	 		num1 <= data;
+  			state <= S2;
+  	 	end else if (state == S2 && data_valid) begin
+  	 		num2 <= data;
+  	 		state <= S3;
+  	 	end else if (state == S3) begin
+  	 		sum <= num1 + num2;
+  	 		flag <= 1'b1;
+  	 		state <= S4;
+  	 	end else if (state == S4) begin
+  	 	  	flag <= 1'b0;
+  	 		state <= S1;
+  	 	end
+  	 end
+  end
+
+endmodule

examples/uart_sum/ffpga/src/top.v

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+module uart_rx #(
+    parameter CLK = 50_000_000,
+    parameter BAUD_RATE = 115200
+) (
+    input         i_Clock,
+    input         i_RX_Serial,
+    output        o_RX_DV, 
+    output [7:0]  o_RX_Byte
+);
+
+parameter CLOCKS_PER_BIT = CLK/BAUD_RATE;
+parameter IDLE = 3'b000;
+parameter RX_START_BIT = 3'b001;
+parameter RX_DATA_BITS = 3'b010;
+parameter RX_STOP_BIT = 3'b011;
+parameter CLEANUP = 3'b100;
+
+reg [17:0] r_Clock_Count;
+reg [2:0] r_Bit_Index;
+reg [7:0] r_RX_Byte;
+reg r_RX_DV;
+reg [2:0] r_SM_Main;
+
+always @(posedge i_Clock) begin
+    case (r_SM_Main)
+        IDLE: begin
+            r_RX_DV <= 1'b0;
+            r_Clock_Count <= 0;
+            r_Bit_Index <= 0;
+
+            if (i_RX_Serial == 1'b0)
+                r_SM_Main <= RX_START_BIT;
+            else
+                r_SM_Main <= IDLE;
+        end
+
+        RX_START_BIT: begin
+            if (r_Clock_Count == CLOCKS_PER_BIT / 2) begin
+                if (i_RX_Serial == 1'b0) begin
+                    r_Clock_Count <= 0;
+                    r_SM_Main <= RX_DATA_BITS;
+                end else
+                    r_SM_Main <= IDLE;
+            end else begin
+                r_Clock_Count <= r_Clock_Count + 1'b1;
+                r_SM_Main <= RX_START_BIT;
+            end
+        end
+
+        RX_DATA_BITS: begin
+            if(r_Clock_Count < CLOCKS_PER_BIT - 1) begin
+                r_Clock_Count <= r_Clock_Count + 1'b1;
+                r_SM_Main <= RX_DATA_BITS;
+            end else begin
+                r_Clock_Count <= 0;
+                r_RX_Byte[r_Bit_Index] <= i_RX_Serial;
+
+                if (r_Bit_Index < 7) begin
+                    r_Bit_Index <= r_Bit_Index + 1'b1;
+                    r_SM_Main <= RX_DATA_BITS;
+                end else begin
+                    r_Bit_Index <= 0;
+                    r_SM_Main <= RX_STOP_BIT;
+                end
+            end
+        end
+
+        RX_STOP_BIT: begin
+            if(r_Clock_Count < CLOCKS_PER_BIT - 1) begin
+                r_Clock_Count <= r_Clock_Count + 1'b1;
+                r_SM_Main <= RX_STOP_BIT;
+            end else begin
+                r_RX_DV <= 1'b1;
+                r_Clock_Count <= 0;
+                r_SM_Main <= CLEANUP;
+            end
+        end
+
+        CLEANUP: begin
+            r_SM_Main <= IDLE;
+            r_RX_DV <= 1'b0;
+        end
+
+        default: r_SM_Main <= IDLE;
+    endcase
+end
+
+assign o_RX_Byte = r_RX_Byte;
+assign o_RX_DV = r_RX_DV;
+
+endmodule