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75a6541
UPSTREAM: riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
RevySR Jul 5, 2025
af1e2bc
UPSTREAM: riscv: dts: sophgo: add ziccrse for sg2042
RevySR Jul 5, 2025
afb462d
UPSTREAM: riscv: dts: sophgo: add zfh for sg2042
RevySR Jul 5, 2025
6d3c077
UPSTREAM: dt-bindings: net: sophgo,sg2044-dwmac: Add support for Soph…
inochisa Jul 8, 2025
50e28f9
UPSTREAM: net: stmmac: dwmac-sophgo: Add support for Sophgo SG2042 SoC
inochisa Jul 8, 2025
b875d4d
UPSTREAM: net: stmmac: platform: Add snps,dwmac-5.00a IP compatible s…
inochisa Jul 8, 2025
7a27d2e
UPSTREAM: riscv: dts: sophgo: add ethernet GMAC device for sg2042
inochisa Jul 8, 2025
c9090f0
UPSTREAM: dt-bindings: soc: sophgo: Move SoCs/boards from riscv into …
sverdlin Jun 12, 2025
6258c5d
UPSTREAM: dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
RevySR Jul 5, 2025
53a7468
UPSTREAM: riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device…
RevySR Jul 5, 2025
bab005c
UPSTREAM: riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device…
RevySR Jul 5, 2025
50b8526
UPSTREAM: spi: dt-bindings: spi-sg2044-nor: Change SOPHGO SG2042
sycamoremoon Jul 20, 2025
858ceda
UPSTREAM: spi: spi-sg2044-nor: Add configurable chip_info
sycamoremoon Jul 20, 2025
fdefcec
UPSTREAM: spi: spi-sg2044-nor: Add SPI-NOR controller for SG2042
sycamoremoon Jul 20, 2025
b87b392
FROMLIST: riscv: mmap(): use unsigned offset type in riscv_sys_mmap
Jul 7, 2025
76a8abc
FROMLIST: riscv: introduce ioremap_wc()
cuiyunhui Jul 22, 2025
1977efe
FROMLIST: drm/ttm: add pgprot handling for RISC-V
Icenowy Jul 22, 2025
740cdfe
FROMLIST: irqchip/sifive-plic: Respect mask state when setting affinity
inochisa Aug 11, 2025
00eee2a
FROMLIST: genirq: Add irq_chip_(startup/shutdown)_parent()
inochisa Aug 13, 2025
8a380ed
FROMLIST: PCI/MSI: Add startup/shutdown for per device domains
inochisa Aug 13, 2025
310f465
FROMLIST: irqchip/sg2042-msi: Fix broken affinity setting
inochisa Aug 13, 2025
5a3c0ff
FROMLIST: irqchip/sg2042-msi: Set MSI_FLAG_MULTI_PCI_MSI flags for SG…
inochisa Aug 13, 2025
bca3e4e
FROMLIST: riscv: Move vendor errata definitions to new header
guoren83 Jul 13, 2025
a86bc18
FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup
guoren83 Jul 13, 2025
ab968b1
FROMLIST: riscv: dts: sophgo: Add SPI NOR node for SG2042
sycamoremoon Aug 13, 2025
2718fa0
FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for PioneerBox
sycamoremoon Aug 13, 2025
8692526
FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1
sycamoremoon Aug 13, 2025
2f8b598
FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2
sycamoremoon Aug 13, 2025
3a7d7ef
FROMLIST: dt-bindings: pci: Add Sophgo SG2042 PCIe host
unicornx Jun 4, 2025
277b9ff
FROMLIST: PCI: sg2042: Add Sophgo SG2042 PCIe driver
unicornx Jun 4, 2025
bcd50eb
FROMLIST: dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible
unicornx Jun 4, 2025
cb61c9d
FROMLIST: riscv: sophgo: dts: add pcie controllers for SG2042
unicornx Jun 4, 2025
920e7dd
FROMLIST: riscv: sophgo: dts: enable pcie for PioneerBox
unicornx Jun 4, 2025
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UPSTREAM: riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device…
… tree

Sophgo SG2042_EVB_V2.0 [1] is a prototype development board based on SG2042

Currently supports serial port, sdcard/emmc, pwm, fan speed control.

Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x4-EVB [1]

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/c1b6ccdc69af0c1457fc1486a6bc8a1e83671537.1751700954.git.rabenda.cn@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit 6ea2a06)
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
  • Loading branch information
RevySR committed Aug 17, 2025
commit bab005c08842695876072a246b79694be228fcf3
1 change: 1 addition & 0 deletions arch/riscv/boot/dts/sophgo/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb
233 changes: 233 additions & 0 deletions arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
Original file line number Diff line number Diff line change
@@ -0,0 +1,233 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 Sophgo Technology Inc. All rights reserved.
*/

#include "sg2042.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
model = "Sophgo SG2042 EVB V2.0";
compatible = "sophgo,sg2042-evb-v2", "sophgo,sg2042";

chosen {
stdout-path = "serial0";
};

pwmfan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <103 128 179 230 255>;
pwms = <&pwm 0 40000 0>;
#cooling-cells = <2>;
};

thermal-zones {
soc-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&mcu 0>;

trips {
soc_active1: soc-active1 {
temperature = <30000>;
hysteresis = <8000>;
type = "active";
};

soc_active2: soc-active2 {
temperature = <58000>;
hysteresis = <12000>;
type = "active";
};

soc_active3: soc-active3 {
temperature = <70000>;
hysteresis = <10000>;
type = "active";
};

soc_hot: soc-hot {
temperature = <80000>;
hysteresis = <5000>;
type = "hot";
};
};

cooling-maps {
map0 {
trip = <&soc_active1>;
cooling-device = <&pwmfan 0 1>;
};

map1 {
trip = <&soc_active2>;
cooling-device = <&pwmfan 1 2>;
};

map2 {
trip = <&soc_active3>;
cooling-device = <&pwmfan 2 3>;
};

map3 {
trip = <&soc_hot>;
cooling-device = <&pwmfan 3 4>;
};
};
};

board-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&mcu 1>;

trips {
board_active: board-active {
temperature = <75000>;
hysteresis = <8000>;
type = "active";
};
};

cooling-maps {
map4 {
trip = <&board_active>;
cooling-device = <&pwmfan 3 4>;
};
};
};
};
};

&cgi_main {
clock-frequency = <25000000>;
};

&cgi_dpll0 {
clock-frequency = <25000000>;
};

&cgi_dpll1 {
clock-frequency = <25000000>;
};

&emmc {
pinctrl-0 = <&emmc_cfg>;
pinctrl-names = "default";
bus-width = <4>;
no-sdio;
no-sd;
non-removable;
wp-inverted;
status = "okay";
};

&i2c1 {
pinctrl-0 = <&i2c1_cfg>;
pinctrl-names = "default";
status = "okay";

mcu: syscon@17 {
compatible = "sophgo,sg2042-hwmon-mcu";
reg = <0x17>;
#thermal-sensor-cells = <1>;
};
};

&gmac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";

mdio {
phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <100000>;
};
};
};

&pinctrl {
emmc_cfg: sdhci-emmc-cfg {
sdhci-emmc-wp-pins {
pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};

sdhci-emmc-cd-pins {
pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};

sdhci-emmc-rst-pwr-pins {
pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
<PINMUX(PIN_EMMC_PWR_EN, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
};

i2c1_cfg: i2c1-cfg {
i2c1-pins {
pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
<PINMUX(PIN_IIC1_SCL, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};

sd_cfg: sdhci-sd-cfg {
sdhci-sd-cd-wp-pins {
pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
<PINMUX(PIN_SDIO_WP, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};

sdhci-sd-rst-pwr-pins {
pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
<PINMUX(PIN_SDIO_PWR_EN, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
};

uart0_cfg: uart0-cfg {
uart0-rx-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};
};

&sd {
pinctrl-0 = <&sd_cfg>;
pinctrl-names = "default";
bus-width = <4>;
no-sdio;
no-mmc;
wp-inverted;
status = "okay";
};

&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
status = "okay";
};