Electronics Engineering @ IIT Madras
Systems Builder • Hardware + Software Integration • AI + Product Engineering

I am a 3rd-year Electronics Engineering student at IIT Madras focused on designing end-to-end systems. I bridge the gap between low-level hardware constraints and high-level software abstraction.

• Hardware–Software Co-design: Verilog, FPGA, and Custom CPU Architectures.
• Embedded Systems: Precision sensing, signal conditioning, and RTOS-like logic.
• AI Engineering: LLM pipelines, RAG, and AI-driven productivity tools.
• Full-Stack: Building scalable platforms with Next.js, Node, and Cloud infra.

• Designed a 3-band active audio equalizer using Multiple Feedback (MFB) filter topology for Bass (100 Hz), Mid (1 kHz), and Treble (4 kHz); implemented precision inverting summing amplifier at near-unity gain (0 dB).
• Hardware measurements confirmed observed Q of 1.52 / 1.36 / 1.22 for Mid/Treble/Bass (designed Q = 1.6); measured center frequencies of 800 Hz, 3 kHz, 110 Hz — deviations attributed to component tolerances via hardware Bode plots.
• Validated via ADALM1000 and oscilloscope; real-audio testing through MATLAB → CSV → hardware → audio

(Jan 2026 – Present)

• Architected a professional-grade diagnostic engine for real-time 12-lead ECG interpretation, featuring multi-stage signal processing and anatomical localization of Myocardial Infarction (STEMI).
• Implemented the Pan-Tompkins QRS Detection Algorithm and Wavelet Denoising (db4) to extract high-precision heart rate, QTc intervals, and HRV (SDNN) metrics from 500Hz raw data streams.
• Developed a deterministic clinical classifier to identify infarct territories (Anterior, Inferior, Lateral) and detect Posterior Wall MI through lead-reciprocity logic in V1–V3 septal leads.
• Engineered a robust backend using FastAPI with strict Pydantic schemas to mirror TypeScript interfaces, ensuring 100% type-safety and data validation for the React-based clinical dashboard.
• Integrated automated clinical report generation using ReportLab, producing structured PDF summaries including signal morphology, confounding factor alerts (LBBB/Pacemaker), and ST-deviation mapping.

• Designed a fully functional single-cycle CPU in Verilog comprising datapath, instruction decode, ALU, register file, memory unit, and control logic.
• Interfaced Ultrasonic (HC-SR04) and DHT11 sensors via GPIO with interrupt-driven I/O for autonomous maze navigation and real-time environmental sensing.
• Verified all modules via simulation testbenches with timing analysis and waveform inspection; confirmed correct operation at 25 MHz on FPGA.

• An end-to-end platform featuring a browser extension (Plasmo) and structured AI learning pipelines.

"Build systems, not just code. Build products, not just projects."