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plan(causaledge64-mailbox-rename-soa-v1): composition spec + 10 epiph…#377
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…anies + plan-index PREPEND

Composes 5 already-authored plans + Σ10 Rubicon doctrine + 1 genuine ndarray-side gap into a single substrate:

  • CausalEdge64 v2 layout — in-place reclaim of 13 reserved bits for G(5) + W(6) + truth(2). No type bump; PAL8 + NarsTables LUT preserved.
  • AttentionMask SoA — session-ephemeral CPU-shaped rename register file (32-slot G, 64-slot W, 256-slot style, 4-level truth). LRU eviction + broadcast notifications. CPU register renaming applied to cognitive identities.
  • MailboxSoA — compartment topology as SoA rows (NOT spawned actors). ~1.5 KB per compartment via shared Arc + tiny delta-buffer
    • outbound CausalEdge64 channel + Option external- intent gate. Supports ~24K parallel thoughts at 200ns cycle speed across <=32 active OGIT domains.
  • TrustTexture/Wisdom/Staunen/MUL truth-band lens collapse — 2 bits with 4 consumer-lens projections. Closes 4 type duplications.
  • SPOW witness emission via gRPC-shape protocol — same Request/Response pair, 4 transport backings (InMemory cycle-speed / Tokio Zone-2 / SupabaseSub Zone-3 / gRPC). Reuse, don't invent.
  • Σ10 Rubicon SigmaTierRouter — wires the named-but-unwired Σ1-Σ10 tier doctrine to runtime mailbox-backing dispatch.
  • Vsa16kF32 retreats from universal-carrier to single-cycle Markov- bundle. Cumulative state moves to AriGraph SPO-G quads + Christmas- tree ghost-edge decoration.
  • Ownership-typed UB-impossibility — borrow checker rejects cross- compartment BindSpace aliasing; race conditions at 200ns become compile errors.

7 PRs sequenced: PR-CE64-MB-1 (par-tile new crate) → 2 (CausalEdge64 v2 layout) + 3 (BindSpace E/F/G/H) + 4 (SPO-G in AriGraph) parallel → 5 (MailboxSoA wiring) → 6 (SigmaTierRouter) → 7 (NdarrayCullPlugin bevy proof). ~6-9 weeks, 3 sprints CCA2A 12-worker fan-out per sprint.

Closes:

Blast radius: 5 crates (par-tile NEW + causal-edge / cognitive-shader- driver / lance-graph-supervisor / lance-graph::arigraph extensions). Zone 3 surface (postgrest / drain / grpc / supabase-realtime) UNTOUCHED. Supabase realtime transcode complemented, not retired.

Iron rules: I-SUBSTRATE-MARKOV preserved + strengthened (Vsa16kF32 retreat); I-VSA-IDENTITIES strengthened (universal-carrier temptation removed); I1 preserved (CollapseGate single mutation point); method-on-carrier discipline preserved (no new free functions).

Board-hygiene per CLAUDE.md: PREPEND INTEGRATION_PLANS.md entry + PREPEND EPIPHANIES.md 10-entry block (E-CE64-MB-1..10). Plan path .claude/plans/causaledge64-mailbox-rename-soa-v1.md. STATUS_BOARD

  • LATEST_STATE updates land per-PR as D-CE64-MB-N rows ship.

Status: Active (draft, pre-execution). 8 OQs at §11 ratify before sprint worker fan-out.

Recursive-eyes acknowledgment: 3rd pair bevy session (diamond + Slice<->Plane bridge + NdarrayCullPlugin proof-first); 4th pair (semantic naming, MultiLaneColumn already named, 5-Layer Stack already named); 5th pair (Vsa16kF32 single-purpose, two-shape ractor, INT4-32D North Star); 6th pair (ephemeral BindSpace + role-as-mailbox + space-time collapse + external-intent gate + Ractor-SoA + Think-as-reference); 7th pair (CausalEdge64-as- emission + truth collapse + 24K parallel thoughts + 12/34/144 hot pattern + zone-naming clarification).

…anies + plan-index PREPEND

Composes 5 already-authored plans + Σ10 Rubicon doctrine + 1 genuine
ndarray-side gap into a single substrate:

* CausalEdge64 v2 layout — in-place reclaim of 13 reserved bits for
  G(5) + W(6) + truth(2). No type bump; PAL8 + NarsTables LUT preserved.
* AttentionMask SoA — session-ephemeral CPU-shaped rename register file
  (32-slot G, 64-slot W, 256-slot style, 4-level truth). LRU eviction +
  broadcast notifications. CPU register renaming applied to cognitive
  identities.
* MailboxSoA — compartment topology as SoA rows (NOT spawned actors).
  ~1.5 KB per compartment via shared Arc<BindSpace> + tiny delta-buffer
  + outbound CausalEdge64 channel + Option<ConsumerHandle> external-
  intent gate. Supports ~24K parallel thoughts at 200ns cycle speed
  across <=32 active OGIT domains.
* TrustTexture/Wisdom/Staunen/MUL truth-band lens collapse — 2 bits
  with 4 consumer-lens projections. Closes 4 type duplications.
* SPOW witness emission via gRPC-shape protocol — same Request/Response
  pair, 4 transport backings (InMemory cycle-speed / Tokio Zone-2 /
  SupabaseSub Zone-3 / gRPC). Reuse, don't invent.
* Σ10 Rubicon SigmaTierRouter — wires the named-but-unwired Σ1-Σ10
  tier doctrine to runtime mailbox-backing dispatch.
* Vsa16kF32 retreats from universal-carrier to single-cycle Markov-
  bundle. Cumulative state moves to AriGraph SPO-G quads + Christmas-
  tree ghost-edge decoration.
* Ownership-typed UB-impossibility — borrow checker rejects cross-
  compartment BindSpace aliasing; race conditions at 200ns become
  compile errors.

7 PRs sequenced: PR-CE64-MB-1 (par-tile new crate) → 2 (CausalEdge64
v2 layout) + 3 (BindSpace E/F/G/H) + 4 (SPO-G in AriGraph) parallel →
5 (MailboxSoA wiring) → 6 (SigmaTierRouter) → 7 (NdarrayCullPlugin
bevy proof). ~6-9 weeks, 3 sprints CCA2A 12-worker fan-out per
sprint.

Closes:
- PR #355 deferred Tier B: FIX-4, FIX-5, per-row BindSpace.context_ids
- THINKING_ORCHESTRATION_WIRING Gap 1 / Gap 3 / Gap 4
- TD-INT4-32D-ATOMS-6 cold-start fallback wiring
- TD-THINKING-ENGINE-UNWIRED-1 (582 KB substrate dormant)

Blast radius: 5 crates (par-tile NEW + causal-edge / cognitive-shader-
driver / lance-graph-supervisor / lance-graph::arigraph extensions).
Zone 3 surface (postgrest / drain / grpc / supabase-realtime) UNTOUCHED.
Supabase realtime transcode complemented, not retired.

Iron rules: I-SUBSTRATE-MARKOV preserved + strengthened (Vsa16kF32
retreat); I-VSA-IDENTITIES strengthened (universal-carrier
temptation removed); I1 preserved (CollapseGate single mutation
point); method-on-carrier discipline preserved (no new free
functions).

Board-hygiene per CLAUDE.md: PREPEND INTEGRATION_PLANS.md entry +
PREPEND EPIPHANIES.md 10-entry block (E-CE64-MB-1..10). Plan path
.claude/plans/causaledge64-mailbox-rename-soa-v1.md. STATUS_BOARD
+ LATEST_STATE updates land per-PR as D-CE64-MB-N rows ship.

Status: Active (draft, pre-execution). 8 OQs at §11 ratify before
sprint worker fan-out.

Recursive-eyes acknowledgment: 3rd pair bevy session (diamond +
Slice<->Plane bridge + NdarrayCullPlugin proof-first); 4th pair
(semantic naming, MultiLaneColumn already named, 5-Layer Stack
already named); 5th pair (Vsa16kF32 single-purpose, two-shape
ractor, INT4-32D North Star); 6th pair (ephemeral BindSpace +
role-as-mailbox + space-time collapse + external-intent gate +
Ractor-SoA + Think-as-reference); 7th pair (CausalEdge64-as-
emission + truth collapse + 24K parallel thoughts + 12/34/144 hot
pattern + zone-naming clarification).
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19-26 O palette index 8 bits same for object
27-42 temporal 16 bits cycle index or temporal window mark
43-50 style ord 8 bits ThinkingStyle ordinal (current 12-base, future 256 hot-slot)
51-63 reserved 13 bits UNUSED today — reclaim target
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P1 Badge Correct the CausalEdge64 bit map before assigning fields

This layout is not the layout in the current crate: crates/causal-edge/src/edge.rs packs S/P/O at bits 0-23, NARS frequency/confidence at 24-39, causal/direction/inference/plasticity at 40-51, and a 12-bit temporal index at 52-63, so bits 51-63 are not zero-default reserved space. If PR-CE64-MB-2 follows this plan, G/W/truth would overwrite existing plasticity/temporal data and break the stated PAL8/binary round-trip and temporal sort invariants rather than being an in-place compatible extension.

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