This check consists in enforcing that the intermediate registers are correctly copied back from the ALU trace to the main trace.
As part of this ticket, we should be able to remove the condition in the main trace enforcing that the values of the intermediate registers is zero when the memory error tag is raised. Instead, we can tolerate in this inter-table relation to not copy the intermediate registers to the ALU whenever the memory error tag is raised. In this way, no relation is enforced on the intermediate registers pertaining the operation.
Adapt the witness generation accordingly.
Note however that the values of intermediate registers will need to be consistent with memory trace.
This check consists in enforcing that the intermediate registers are correctly copied back from the ALU trace to the main trace.
As part of this ticket, we should be able to remove the condition in the main trace enforcing that the values of the intermediate registers is zero when the memory error tag is raised. Instead, we can tolerate in this inter-table relation to not copy the intermediate registers to the ALU whenever the memory error tag is raised. In this way, no relation is enforced on the intermediate registers pertaining the operation.
Adapt the witness generation accordingly.
Note however that the values of intermediate registers will need to be consistent with memory trace.