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odroid_h4 config: set edk2 rev to odroid v0.9.1 sb user mode fix #723

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odroid_h4 config: set edk2 rev to odroid v0.9.1 sb user mode fix #723

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155fd50
mb/hardkernel/odroid-h4: Add netcard support
miczyg1 May 21, 2025
eebc508
mb/hardkernel/odroid-h4/data.vbt: Update VBT for newest FSP GOP
miczyg1 Jun 10, 2025
f35bfde
configs/config.hardkernel_odroid_h4: Enable quiet and fast boot
miczyg1 May 21, 2025
6ea61ec
configs/config.hardkernel_odroid_h4: Enable ME configuration menu
miczyg1 May 21, 2025
28a562f
mb/hardkernel/odroid-h4/devicetree.cb: Disable DSP
miczyg1 Jun 10, 2025
d683707
vendorcode/dasharo,soc/intel: Add IBECC option
miczyg1 May 22, 2025
33c0270
mainboard/hardkernel/odroid-h4: Add IBECC configuration
miczyg1 May 22, 2025
94d491b
payloads/external/edk2: Add IBECC option support
miczyg1 May 22, 2025
8e31fdf
configs/{msi,hardkernel}: Update configs for new memory menu PCDs
miczyg1 May 22, 2025
0595702
configs/config.hardkernel_odroid_h4: Enable FW performance measurement
miczyg1 Jun 11, 2025
b262578
.github/workflows/build.yml: Build netcard variant of ODROID
miczyg1 Jun 16, 2025
a8a091d
configs/config.hardkernel_odroid_h4: Bump to v0.9.1-rc1
miczyg1 Jun 16, 2025
c93ea29
odroid_h4 config: set edk2 rev to odroid v0.9.1 sb user mode fix
philipanda Jul 25, 2025
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vendorcode/dasharo,soc/intel: Add IBECC option 
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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@miczyg1
miczyg1 committed Jun 16, 2025
commit d68370750e98fcf15084119b26c6cf8986482a55
4 changes: 2 additions & 2 deletions src/soc/intel/alderlake/romstage/fsp_params.c
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Expand Up @@ -397,8 +397,8 @@ static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_alderlake_config *config)
{
/* In-Band ECC configuration */
if (config->ibecc.enable) {
m_cfg->Ibecc = config->ibecc.enable;
if (get_ibecc_option(config->ibecc.enable)) {
m_cfg->Ibecc = 1;
m_cfg->IbeccOperationMode = config->ibecc.mode;
if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) {
FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeEnable,
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7 changes: 4 additions & 3 deletions src/soc/intel/elkhartlake/romstage/fsp_params.c
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Expand Up @@ -2,6 +2,7 @@

#include <assert.h>
#include <console/console.h>
#include <dasharo/options.h>
#include <device/device.h>
#include <fsp/util.h>
#include <intelblocks/cpulib.h>
Expand Down Expand Up @@ -99,9 +100,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* Processor Early Power On Configuration FCLK setting */
m_cfg->FClkFrequency = 0x1;

/* Ib-Band ECC configuration */
if (config->ibecc.enable) {
m_cfg->Ibecc = !!config->ibecc.enable;
/* In-Band ECC configuration */
if (get_ibecc_option(config->ibecc.enable)) {
m_cfg->Ibecc = 1;
m_cfg->IbeccParity = !!config->ibecc.parity_en;
m_cfg->IbeccOperationMode = config->ibecc.mode;
if (m_cfg->IbeccOperationMode == IBECC_PER_REGION) {
Expand Down
4 changes: 2 additions & 2 deletions src/soc/intel/meteorlake/romstage/fsp_params.c
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Expand Up @@ -395,8 +395,8 @@ static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_meteorlake_config *config)
{
/* In-Band ECC configuration */
if (config->ibecc.enable) {
m_cfg->Ibecc = config->ibecc.enable;
if (get_ibecc_option(config->ibecc.enable)) {
m_cfg->Ibecc = 1;
m_cfg->IbeccParity = config->ibecc.parity_en;
m_cfg->IbeccOperationMode = config->ibecc.mode;
if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) {
Expand Down
4 changes: 2 additions & 2 deletions src/soc/intel/tigerlake/romstage/fsp_params.c
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Expand Up @@ -212,8 +212,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice;

/* In-Band ECC configuration */
if (config->ibecc.enable) {
m_cfg->Ibecc = !!config->ibecc.enable;
if (get_ibecc_option(config->ibecc.enable)) {
m_cfg->Ibecc = 1;
m_cfg->IbeccParity = !!config->ibecc.parity_en;
m_cfg->IbeccOperationMode = config->ibecc.mode;
if (m_cfg->IbeccOperationMode == IBECC_PER_REGION) {
Expand Down
13 changes: 12 additions & 1 deletion src/vendorcode/dasharo/include/dasharo/options.h
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Original file line number Diff line number Diff line change
Expand Up @@ -314,6 +314,17 @@ uint8_t get_cpu_throttling_offset(uint8_t tcc_offset);
* - 1 - NVIDIA Optimus (iGPU + dGPU)
* - 2 - dGPU only
*/
enum dgpu_state dasharo_dgpu_state(void);
enum dgpu_state dasharo_dgpu_state(void);

/* Looks Dasharo/"IBECC" variable to check In-Band ECC should be
* enabled.
*
* Arguments:
* - default - default platform value of IBECC
* Result:
* - true - In-Band ECC enabled
* - false - In-Band ECC disabled
*/
bool get_ibecc_option(bool ibecc_default);

#endif /* DASHARO_OPTIONS_H */
10 changes: 10 additions & 0 deletions src/vendorcode/dasharo/options.c
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Expand Up @@ -530,3 +530,13 @@ uint8_t get_cpu_throttling_offset(uint8_t tcc_offset)

return offset;
}

bool get_ibecc_option(bool ibecc_default)
{
bool ibecc_en = ibecc_default;

if (CONFIG(DRIVERS_EFI_VARIABLE_STORE))
read_bool_var("IBECC", &ibecc_en);

return ibecc_en;
}