GlassROM-devices · ghost · Mar 11, 2016 · Mar 12, 2014 · Jun 18, 2014 · Apr 14, 2015
diff --git a/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt b/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt
@@ -71,8 +71,6 @@ Required properties:
 	sleep.
 	- qcom,last-level - When set, the cluster level is applied only when
 	there is 1 online core.
-	- qcom,disable-dynamic-int-routing: When set disables the dynamic
-	routing of rpm-smd and mpm interrupts to next wake up core.
 
 [Node bindings for qcom,pm-cpu]
 qcom,pm-cpu contains the low power modes that a cpu could enter. Currently it

diff --git a/Documentation/devicetree/bindings/arm/msm/lpm-workarounds.txt b/Documentation/devicetree/bindings/arm/msm/lpm-workarounds.txt
@@ -5,11 +5,6 @@ The required properties are:
 - compatible: "qcom,lpm-workarounds"
 
 The optional properties are:
-- reg: The physical address and the size of the l1_l2_gcc and l2_pwr_sts
-	regitsters of performance cluster.
-
-- reg-names: "l2_pwr_sts" - string to identify l2_pwr_sts physical address.
-	     "l1_l2_gcc" - string to identify l1_l2_gcc physical address.
 
 - qcom,lpm-wa-cx-turbo-unvote: Indicates the workaround to unvote CX turbo
 	vote when system is coming out of rpm assisted power collaspe.
@@ -18,36 +13,11 @@ The optional properties are:
 - lpm-cx-supply:  will hold handle for CX regulator supply which is used
 	to unvote.
 
-- qcom,lpm-wa-skip-l2-spm: Due to a hardware bug on 8939 and 8909, secure
-	world needs to disable and enable L2 SPM to get the proper context
-	in secure watchdog bite cases. With this workaround there is a race
-	in programming L2 SPM between HLOS and secure world. This leads to
-	stability issues. To avoid this program L2 SPM only in secure world
-	based on the L2 mode flag passed. Set lpm-wa-skip-l2-spm node if this
-	is required.
-
-- qcom,lpm-wa-dynamic-clock-gating: Due to a hardware bug on 8952, L1/L2 dynamic
-	clock gating needs to be enabled by software for performance cluster
-	cores and L2. Set lpm-wa-dynamic-clock-gating node if this workaround is
-	required.
-
-- qcom,cpu-offline-mask: Dynamic clock gating should be enabled when cluster is
-	in L2 PC. Each bit of cpu-offline-mask lists the cpu no. to hotplug by KTM
-	driver.
-
-- qcom,non-boot-cpu-index: will hold index of non boot cluster cpu.
-
 Example:
 
 qcom,lpm-workarounds {
 	compatible = "qcom,lpm-workarounds";
-	reg = <0x0B011018 0x4>,
-	      <0x0B011088 0x4>;
-	reg-names = "l2-pwr-sts", "l1-l2-gcc";
+
 	lpm-cx-supply = <&pm8916_s2_corner>;
 	qcom,lpm-wa-cx-turbo-unvote;
-	qcom,lpm-wa-skip-l2-spm;
-	qcom,lpm-wa-dynamic-clock-gating;
-	qcom,cpu-offline-mask = "0xF";
-	qcom,non-boot-cpu-index = <4>;
 }
diff --git a/Makefile b/Makefile
@@ -380,7 +380,7 @@ CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
 CFLAGS_MODULE   = $(FLAGS_OPTIMIZE) $(GRAPHITE)
 AFLAGS_MODULE   = $(FLAGS_OPTIMIZE) $(GRAPHITE)
 LDFLAGS_MODULE  = --strip-debug
-CFLAGS_KERNEL	= $(FLAGS_OPTIMIZE) $(GRAPHITE) -mcpu=cortex-a57.cortex-a53+crypto+crc -mtune=cortex-a57.cortex-a53 -march=armv8-a+crypto+crc
+CFLAGS_KERNEL	= $(FLAGS_OPTIMIZE) $(GRAPHITE) -mcpu=cortex-a57.cortex-a53+crypto+crc -mtune=cortex-a57.cortex-a53 -march=armv8-a+crypto+crc -mfix-cortex-a53-843419 -mfix-cortex-a53-835769 
 AFLAGS_KERNEL	= $(FLAGS_OPTIMIZE) $(GRAPHITE)
 CFLAGS_GCOV	= -fprofile-arcs -ftest-coverage
 
@@ -437,6 +437,8 @@ KBUILD_CFLAGS   := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
 		   -Wno-switch-bool \
 		   -Wno-multistatement-macros \
 		   -Wno-bool-operation -Wno-nonnull -Wno-switch-unreachable -Wno-format-truncation -Wno-format-overflow -Wno-duplicate-decl-specifier -Wno-memset-elt-size -Wno-int-in-bool-context \
+		   -mstrict-align \
+		   -mfix-cortex-a53-843419 -mfix-cortex-a53-835769 \
 		   $(GEN_OPT_FLAGS) \
 		   $(GRAPHITE) \
 		   $(FLAGS_OPTIMIZE)

diff --git a/android/configs/android-recommended.cfg b/android/configs/android-recommended.cfg
@@ -109,6 +109,10 @@ CONFIG_TABLET_USB_GTCO=y
 CONFIG_TABLET_USB_HANWANG=y
 CONFIG_TABLET_USB_KBTAB=y
 CONFIG_TABLET_USB_WACOM=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASK_XACCT=y
 CONFIG_TIMER_STATS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y

diff --git a/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi b/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi
@@ -608,6 +608,8 @@
 			label = "rgb";
 			status = "okay";
 
+			qcom,rgb-sync;
+
 			qcom,rgb_0 {
 				label = "rgb";
 				qcom,id = <3>;

diff --git a/arch/arm/boot/dts/qcom/msm8994.dtsi b/arch/arm/boot/dts/qcom/msm8994.dtsi
@@ -37,9 +37,17 @@
 					dev = "/dev/block/platform/soc.0/f9824900.sdhci/by-name/system";
 					type = "ext4";
 					mnt_flags = "ro,barrier=1,discard";
-					fsmgr_flags = "wait";
+					fsmgr_flags = "wait,verify=/dev/block/platform/soc.0/f9824900.sdhci/by-name/reserve2";
 					status = "ok";
 				};
+vendor {
+      compatible = "android,vendor";
+      dev = "/dev/block/platform/soc.0/f9824900.sdhci/by-name/cache";
+      type = "ext4";
+      mnt_flags = "ro,barrier=1,discard";
+					fsmgr_flags = "wait,verify=/dev/block/platform/soc.0/f9824900.sdhci/by-name/reserve2";
+      status = "ok";
+    };
 			};
 		};
 	};

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
@@ -160,6 +160,8 @@ static void arm_dma_unremap(struct device *dev, void *remapped_addr,
 		return;
 	}
 	vunmap(remapped_addr);
+	flush_tlb_kernel_range((unsigned long)remapped_addr,
+			(unsigned long)(remapped_addr + size));
 }
 
 struct dma_map_ops arm_dma_ops = {

diff --git a/arch/arm64/configs/haruhi_defconfig b/arch/arm64/configs/haruhi_defconfig
@@ -598,14 +598,22 @@ CONFIG_DEFAULT_WESTWOOD=y
 CONFIG_DEFAULT_TCP_CONG="westwood"
 CONFIG_WIREGUARD=y
 # CONFIG_WIREGUARD_DEBUG is not set
-CONFIG_FB_MSM_MDSS_KCAL_CTRL=y
 CONFIG_CRYPTO_SHA256_ARM64=y
 CONFIG_CRYPTO_SHA512_ARM64=y
 CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
-CONFIG_QUICK_WAKEUP=y
-CONFIG_POWERSUSPEND=y
 # CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set
 # CONFIG_TCP_CONG_BIC is not set
 # CONFIG_TCP_CONG_CUBIC is not set
 # CONFIG_TCP_CONG_HTCP is not set
 CONFIG_EXFAT_FS=y
+CONFIG_SDFAT_FS=y
+CONFIG_SDFAT_DELAYED_META_DIRTY=y
+CONFIG_SDFAT_SUPPORT_DIR_SYNC=y
+CONFIG_SDFAT_DEFAULT_CODEPAGE=437
+CONFIG_SDFAT_DEFAULT_IOCHARSET="utf8"
+CONFIG_SDFAT_ALIGNED_MPAGE_WRITE=y
+CONFIG_SDFAT_VIRTUAL_XATTR=y
+CONFIG_SDFAT_VIRTUAL_XATTR_SELINUX_LABEL="u:object_r:vfat:s0"
+CONFIG_SDFAT_DEBUG=y
+CONFIG_SDFAT_DBG_MSG=y
+CONFIG_SDFAT_STATISTICS=y
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
@@ -506,6 +506,8 @@ static void arm64_dma_unremap(struct device *dev, void *remapped_addr,
 		return;
 	}
 	vunmap(remapped_addr);
+	flush_tlb_kernel_range((unsigned long)remapped_addr,
+			(unsigned long)(remapped_addr + size));
 }
 
 const struct dma_map_ops noncoherent_swiotlb_dma_ops = {

diff --git a/crypto/hmac.c b/crypto/hmac.c
@@ -197,11 +197,15 @@ static int hmac_create(struct crypto_template *tmpl, struct rtattr **tb)
 	salg = shash_attr_alg(tb[1], 0, 0);
 	if (IS_ERR(salg))
 		return PTR_ERR(salg);
+	alg = &salg->base;
 
+	/* The underlying hash algorithm must be unkeyed */
 	err = -EINVAL;
+	if (crypto_shash_alg_has_setkey(salg))
+		goto out_put_alg;
+
 	ds = salg->digestsize;
 	ss = salg->statesize;
-	alg = &salg->base;
 	if (ds > alg->cra_blocksize ||
 	    ss < alg->cra_blocksize)
 		goto out_put_alg;

diff --git a/crypto/shash.c b/crypto/shash.c
@@ -24,11 +24,12 @@
 
 static const struct crypto_type crypto_shash_type;
 
-static int shash_no_setkey(struct crypto_shash *tfm, const u8 *key,
-			   unsigned int keylen)
+int shash_no_setkey(struct crypto_shash *tfm, const u8 *key,
+		    unsigned int keylen)
 {
 	return -ENOSYS;
 }
+EXPORT_SYMBOL_GPL(shash_no_setkey);
 
 static int shash_setkey_unaligned(struct crypto_shash *tfm, const u8 *key,
 				  unsigned int keylen)