Migrate to use BRAM

.github/workflows/difftest-selfhost.yml

@@ -0,0 +1,55 @@
+name: Self-hosted Difftest
+
+on:
+  push:
+    branches: [main]
+  pull_request:
+    branches: [main]
+  workflow_dispatch:
+
+jobs:
+  difftest:
+    runs-on: self-hosted
+
+    steps:
+      - uses: actions/checkout@v3
+
+      - name: Clone Chiplab Repo
+        uses: actions/checkout@v3
+        with:
+          repository: Invalid-Syntax-NSCSCC/min-chiplab
+          token: ${{ secrets.DIFFTEST_ACCESS_TOKEN }}
+          path: chiplab
+
+      - name: Prepare Environment
+        run: |
+          echo "`pwd`/chiplab/toolchains/loongarch32r-linux-gnusf-2022-05-20/bin" >> $GITHUB_PATH
+
+      - name: Use Cache
+        uses: coursier/cache-action@v6
+
+      - name: Elaborate CPU
+        run: make
+
+      - name: Move to Chiplab
+        run: |
+          export CHIPLAB_HOME=`pwd`/chiplab
+          make chiplab
+
+      - name: Test
+        run: |
+          export CHIPLAB_HOME=`pwd`/chiplab
+          ./chiplab/sims/verilator/run_prog/configure.sh --run func/func_lab8 --tail-waveform --tail-simu-trace --waveform-tail-size 200 --trace-tail-size 200
+          cd ./chiplab/sims/verilator/run_prog
+          make -j`nproc` > make_log.txt 2>&1
+          sed -i '/RUN simulation/,$!d' make_log.txt
+          cat make_log.txt
+
+      - name: Upload Result
+        uses: actions/upload-artifact@v3
+        with:
+          name: difftest-log
+          path: |
+            ./chiplab/sims/verilator/run_prog/make_log.txt
+            ./chiplab/sims/verilator/run_prog/log/**/simu_trace.*
+            ./chiplab/sims/verilator/run_prog/obj/**/obj/test.s

.scalafmt.conf

@@ -43,4 +43,4 @@ verticalMultiline.atDefnSite = true
 
 optIn.annotationNewlines = true
 
-rewrite.rules = [SortImports, PreferCurlyFors, AvoidInfix]
+rewrite.rules = [SortImports, PreferCurlyFors, AvoidInfix]

src/src/memory/BRam.scala

@@ -15,7 +15,7 @@ class BRam(size: Int, dataWidth: Int) extends Module {
     val dataOut = Output(UInt(dataWidth.W))
   })
 
-  val data = RegInit(VecInit(Seq.fill(size)(0.U(dataWidth.W))))
+  val data = Reg(Vec(size, UInt(dataWidth.W)))
 
   // Read
   io.dataOut := RegNext(data(io.addr))