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Merged
Chrisqcwx merged 2 commits into from
Jun 19, 2023
Merged

Refactor csr #149

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fa5cf54
refactor: kill all Cats in Csr
Chrisqcwx Jun 19, 2023
5ed0385
fix: csr parameters
Chrisqcwx Jun 19, 2023
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89 changes: 38 additions & 51 deletions src/src/control/Csr.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -10,10 +10,6 @@ import common.bundles.RfReadPort
import control.csrRegsBundles._
import spec.Param.isDiffTest

// TODO: 中断：ecfg, estat.is
// TODO: 同时读写csrRegs时候读端口的赋值
// TODO: TLB相关寄存器
// TODO: 计时器中断
class Csr(
writeNum: Int = Param.csrRegsWriteNum,
readNum: Int = Param.csrRegsReadNum)
Expand Down Expand Up @@ -146,7 +142,7 @@ class Csr(
when(tval.out.timeVal === 0.U) {
tval.in.timeVal := Mux(
tcfg.out.periodic,
Cat(tcfg.out.initVal, 0.U(2.W)),
tcfg.out.initVal << 2,
"hffffffff".U(32.W)
)
estat.in.is_timeInt := true.B
Expand All @@ -170,13 +166,14 @@ class Csr(
crmd.in.datm := writePort.data(8, 7)
}
is(spec.Csr.Index.prmd) {
prmd.in := Cat(0.U(29.W), writePort.data(2, 0)).asTypeOf(prmd.in)
prmd.in.pplv := writePort.data(1, 0)
prmd.in.pie := writePort.data(2)
}
is(spec.Csr.Index.euen) {
euen.in := Cat(0.U(31.W), writePort.data(0)).asTypeOf(euen.in)
euen.in.fpe := writePort.data(0)
}
is(spec.Csr.Index.ecfg) {
ecfg.in := Cat(0.U(19.W), writePort.data(12, 0)).asTypeOf(ecfg.in)
ecfg.in.lie := writePort.data(12, 0)
}
is(spec.Csr.Index.estat) {
estat.in.is_softwareInt := writePort.data(1, 0)
Expand Down Expand Up @@ -217,7 +214,7 @@ class Csr(
tid.in := writePort.data.asTypeOf(tid.in)
}
is(spec.Csr.Index.eentry) {
eentry.in := Cat(writePort.data(31, 6), 0.U(6.W)).asTypeOf(eentry.in)
eentry.in.va := writePort.data(31, 6)
}
is(spec.Csr.Index.cpuid) {
// no write
Expand All @@ -229,30 +226,28 @@ class Csr(
}
}
is(spec.Csr.Index.tlbidx) {
tlbidx.in := Cat(
writePort.data(31),
false.B,
writePort.data(29, 24),
0.U((24 - spec.Csr.Tlbidx.Width.index).W),
writePort.data(spec.Csr.Tlbidx.Width.index - 1, 0)
).asTypeOf(tlbidx.in)
tlbidx.in.index := writePort.data(spec.Csr.Tlbidx.Width.index - 1, 0)
tlbidx.in.ps := writePort.data(29, 24)
tlbidx.in.ne := writePort.data(31)
}
is(spec.Csr.Index.tlbehi) {
tlbehi.in := Cat(writePort.data(31, 13), 0.U(13.W)).asTypeOf(tlbehi.in)
tlbehi.in.vppn := writePort.data(31, 13)
}
is(spec.Csr.Index.tlbelo0) {
tlbelo0.in := Cat(
writePort.data(31, 8),
false.B,
writePort.data(6, 0)
).asTypeOf(tlbelo0.in)
tlbelo0.in.v := writePort.data(0)
tlbelo0.in.d := writePort.data(1)
tlbelo0.in.plv := writePort.data(3, 2)
tlbelo0.in.mat := writePort.data(5, 4)
tlbelo0.in.g := writePort.data(6)
tlbelo0.in.ppn := writePort.data(spec.Csr.Tlbelo.Width.palen - 5, 8)
}
is(spec.Csr.Index.tlbelo1) {
tlbelo1.in := Cat(
writePort.data(31, 8),
false.B,
writePort.data(6, 0)
).asTypeOf(tlbelo1.in)
tlbelo1.in.v := writePort.data(0)
tlbelo1.in.d := writePort.data(1)
tlbelo1.in.plv := writePort.data(3, 2)
tlbelo1.in.mat := writePort.data(5, 4)
tlbelo1.in.g := writePort.data(6)
tlbelo1.in.ppn := writePort.data(spec.Csr.Tlbelo.Width.palen - 5, 8)
}
is(spec.Csr.Index.asid) {
asid.in.asid := writePort.data(9, 0)
Expand All @@ -261,42 +256,34 @@ class Csr(
// no write
}
is(spec.Csr.Index.pgdl) {
pgdl.in := Cat(writePort.data(31, 12), 0.U(12.W)).asTypeOf(pgdl.in)
pgdl.in.base := writePort.data(31, 12)
}
is(spec.Csr.Index.pgdh) {
pgdh.in := Cat(writePort.data(31, 12), 0.U(12.W)).asTypeOf(pgdh.in)
pgdh.in.base := writePort.data(31, 12)
}
is(spec.Csr.Index.tlbrentry) {
tlbrentry.in := Cat(writePort.data(31, 6), 0.U(6.W)).asTypeOf(tlbrentry.in)
tlbrentry.in.pa := writePort.data(31, 6)
}
is(spec.Csr.Index.dmw0) {
dmw0.in := Cat(
writePort.data(31, 29),
false.B,
writePort.data(27, 25),
0.U(19.W),
writePort.data(5, 3),
0.U(2.W),
writePort.data(0)
).asTypeOf(dmw0.in)
dmw0.in.plv0 := writePort.data(0)
dmw0.in.plv3 := writePort.data(3)
dmw0.in.mat := writePort.data(5, 4)
dmw0.in.pseg := writePort.data(27, 25)
dmw0.in.vseg := writePort.data(31, 29)
}
is(spec.Csr.Index.dmw1) {
dmw1.in := Cat(
writePort.data(31, 29),
false.B,
writePort.data(27, 25),
0.U(19.W),
writePort.data(5, 3),
0.U(2.W),
writePort.data(0)
).asTypeOf(dmw1.in)
dmw1.in.plv0 := writePort.data(0)
dmw1.in.plv3 := writePort.data(3)
dmw1.in.mat := writePort.data(5, 4)
dmw1.in.pseg := writePort.data(27, 25)
dmw1.in.vseg := writePort.data(31, 29)
}
is(spec.Csr.Index.tcfg) {
val initVal = WireDefault(writePort.data(spec.Csr.TimeVal.Width.timeVal - 1, 2))
tcfg.in.initVal := initVal
tcfg.in.periodic := writePort.data(1)
tcfg.in.en := writePort.data(0)
tval.in.timeVal := Cat(initVal, 0.U(2.W))
tval.in.timeVal := initVal << 2
}
is(spec.Csr.Index.tval) {
// no write
Expand Down Expand Up @@ -370,8 +357,8 @@ class Csr(
}

// 中断
// la 空出来了一位
estat.in.is_hardwareInt := Cat(false.B, io.csrMessage.hardWareInetrrupt)
// la 最高位空出来了一位
estat.in.is_hardwareInt := io.csrMessage.hardWareInetrrupt

val hasInterrupt = ((estat.out.asUInt)(12, 0) & ecfg.out.lie(12, 0)).orR && crmd.out.ie
io.hasInterrupt := hasInterrupt && !RegNext(hasInterrupt)
Expand Down
5 changes: 0 additions & 5 deletions src/src/control/Cu.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,7 @@ import spec.{Csr, ExeInst, Param, PipelineStageIndex}
import spec.Param.isDiffTest
import control.bundles.BranchFlushInfo

// TODO: Add stall to frontend ?
// TODO: Add deal exceptions
// TODO: 出错虚地址badv的赋值
// TODO: 处理break和syscall指令
// 优先解决多发射中index小的流水线
// Attention: ll与sc指令只能从第0条流水线发射（按满洋的设计）
class Cu(
ctrlControlNum: Int = Param.ctrlControlNum,
writeNum: Int = Param.csrRegsWriteNum,
Expand Down
2 changes: 1 addition & 1 deletion src/src/control/csrRegsBundles/TlbeloBundle.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ import chisel3.experimental.BundleLiterals._
import spec._

class TlbeloBundle extends Bundle {
val ppn = UInt(24.W)
val ppn = UInt((spec.Csr.Tlbelo.Width.palen - 12).W)
val zero = Bool()
val g = Bool()
val mat = UInt(2.W)
Expand Down
10 changes: 7 additions & 3 deletions src/src/spec/Csr.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -118,15 +118,19 @@ object Csr {

object TimeVal {
object Width {
// 待修改
val timeVal = 32
}
}

object Tlbidx {
object Width {
// Attention: 这与TLB实现有关，待修改
val index = 12
val index = log2Ceil(Param.Count.Tlb.num)
}
}

object Tlbelo {
object Width {
val palen = spec.Width.Mem._addr
}
}

Expand Down