Invalid-Syntax-NSCSCC · rewired-gh · Jun 24, 2023 · Jun 24, 2023 · Jun 24, 2023
diff --git a/src/src/CoreCpuTop.scala b/src/src/CoreCpuTop.scala
@@ -96,12 +96,11 @@ class CoreCpuTop extends Module {
       else None
   })
 
-  val iCache         = Module(new ICache)
-  val frontend       = Module(new Frontend)
-  val instQueue      = Module(new MultiInstQueue)
-  val issueStage     = Module(new IssueStage)
-  val exeForMemStage = Module(new ExeForMemStage)
-  // val exePassWbStages = Seq.fill(Param.exePassWbNum)(Module(new ExePassWbStage))
+  val iCache           = Module(new ICache)
+  val frontend         = Module(new Frontend)
+  val instQueue        = Module(new MultiInstQueue)
+  val issueStage       = Module(new IssueStage)
+  val exeForMemStage   = Module(new ExeForMemStage)
   val exePassWbStage_1 = Module(new ExePassWbStage(supportBranchCsr = true))
   val exePassWbStage_2 = Module(new ExePassWbStage(supportBranchCsr = false))
   val exePassWbStages  = Seq(exePassWbStage_1, exePassWbStage_2)
@@ -116,16 +115,14 @@ class CoreCpuTop extends Module {
   val memReqStage    = Module(new MemReqStage)
   val memResStage    = Module(new MemResStage)
 
-  // pass through
+  // Passthrough
   memReqStage.io.out.ready := true.B
   exePassWbStages.foreach(_.io.out.ready := true.B)
 
   val crossbar = Module(new Axi3x1Crossbar)
 
   val csrScoreBoard = Module(new CsrScoreboard)
 
-  // val dataforward = Module(new DataForwardStage)
-
   val regFile = Module(new RegFile)
   val pc      = Module(new Pc)
 
@@ -136,7 +133,7 @@ class CoreCpuTop extends Module {
   // AXI top <> AXI crossbar
   crossbar.io.master(0) <> io.axi
 
-  // `ICache` <> AXI crossbar
+  // ICache <> AXI crossbar
   crossbar.io.slave(0) <> iCache.io.axiMasterPort
 
   // Memory related modules
@@ -196,30 +193,11 @@ class CoreCpuTop extends Module {
     case (dst, src) =>
       dst := src
   }
-  // issueStage.io.peer.get.robInstValids.zip(rob.io.robInstValids).foreach {
-  //   case (dst, src) =>
-  //     dst := src
-  // }
-
-  // def connect_wb(dst: InstWbNdPort, src: DecoupledIO[WbNdPort]): Unit = {
-  //   dst.en    := src.valid
-  //   dst.data  := src.bits.gprWrite.data
-  //   dst.robId := src.bits.instInfo.robId
-  // }
-  // issueStage.io.peer.get.writebacks.zipWithIndex.foreach {
-  //   case (dst, idx) =>
-  //     assert(Param.loadStoreIssuePipelineIndex == 0, "if load store no issue in line 0, please change if-else below")
-  //     if (idx == Param.loadStoreIssuePipelineIndex) {
-  //       connect_wb(dst, memResStage.io.out)
-  //     } else {
-  //       connect_wb(dst, exePassWbStages(idx - 1).io.out)
-  //     }
-  // }
   issueStage.io.peer.get.writebacks.zip(rob.io.instWbBroadCasts).foreach {
     case (dst, src) =>
       dst := src
   }
-  issueStage.io.peer.get.csrRegScore := csrScoreBoard.io.regScore
+  issueStage.io.peer.get.csrcore     := csrScoreBoard.io.regScore
   issueStage.io.peer.get.csrReadPort <> csr.io.readPorts(0)
 
   // Scoreboards
@@ -289,9 +267,8 @@ class CoreCpuTop extends Module {
     case (dst, src) =>
       dst <> src
   }
-  commitStage.io.csrValues := csr.io.csrValues
 
-  // regfile
+  // Reg file
   regFile.io.writePorts <> cu.io.gprWritePassThroughPorts.out
   regFile.io.readPorts.zip(rob.io.regReadPortss).foreach {
     case (rfReads, robReads) =>
@@ -301,7 +278,7 @@ class CoreCpuTop extends Module {
       }
   }
 
-  // Ctrl unit
+  // Control unit
   cu.io.instInfoPorts.zip(commitStage.io.cuInstInfoPorts).foreach {
     case (dst, src) => dst := src
   }
@@ -310,10 +287,6 @@ class CoreCpuTop extends Module {
   }
   cu.io.csrValues             := csr.io.csrValues
   cu.io.stableCounterReadPort <> stableCounter.io
-  // cu.io.robInstValids.zip(rob.io.robInstValids).foreach {
-  //   case (dst, src) =>
-  //     dst := src
-  // }
 
   require(Param.jumpBranchPipelineIndex != 0)
   cu.io.branchExe    := exePassWbStages(Param.jumpBranchPipelineIndex - 1).io.peer.get.branchSetPort.get
@@ -322,12 +295,11 @@ class CoreCpuTop extends Module {
   cu.io.hardWareInetrrupt := io.intrpt
 
   // After memory request flush connection
-  // memReqStage.io.peer.get.isAfterMemReqFlush := cu.io.isAfterMemReqFlush
   cu.io.isExceptionValidVec(0) := false.B // memReqStage.io.peer.get.isExceptionValid
   cu.io.isExceptionValidVec(1) := false.B // memResStage.io.peer.get.isExceptionValid
   cu.io.isExceptionValidVec(2) := commitStage.io.isExceptionValid
 
-  // Csr
+  // CSR
   csr.io.writePorts.zip(cu.io.csrWritePorts).foreach {
     case (dst, src) =>
       dst := src

diff --git a/src/src/control/Csr.scala b/src/src/control/Csr.scala
@@ -3,20 +3,20 @@ package control
 import chisel3._
 import chisel3.util._
 import control.bundles._
-import control.csrRegsBundles._
+import control.csrBundles._
 import spec._
 
 class Csr(
-  writeNum: Int = Param.csrRegsWriteNum,
-  readNum:  Int = Param.csrRegsReadNum)
+  writeNum: Int = Param.csrWriteNum,
+  readNum:  Int = Param.csrReadNum)
     extends Module {
   val io = IO(new Bundle {
     // `Cu` -> `Csr`
     val writePorts = Input(Vec(writeNum, new CsrWriteNdPort))
     val csrMessage = Input(new CuToCsrNdPort)
     val csrValues  = Output(new CsrValuePort)
     // `Csr` <-> `RegReadStage`
-    val readPorts = Vec(Param.csrRegsReadNum, new CsrReadPort)
+    val readPorts = Vec(Param.csrReadNum, new CsrReadPort)
     // `Csr` -> `WbStage`
     val hasInterrupt = Output(Bool())
   })
@@ -35,98 +35,98 @@ class Csr(
     passPort
   }
 
-  val csrRegs = RegInit(VecInit(Seq.fill(Count.csrReg)(zeroWord)))
+  val csr = RegInit(VecInit(Seq.fill(Count.csrReg)(zeroWord)))
 
   // CRMD 当前模式信息
 
-  val crmd = viewUInt(csrRegs(spec.Csr.Index.crmd), new CrmdBundle)
+  val crmd = viewUInt(csr(spec.Csr.Index.crmd), new CrmdBundle)
 
   // PRMD 例外前模式信息
-  val prmd = viewUInt(csrRegs(spec.Csr.Index.prmd), new PrmdBundle)
+  val prmd = viewUInt(csr(spec.Csr.Index.prmd), new PrmdBundle)
 
   // EUEN扩展部件使能
-  val euen = viewUInt(csrRegs(spec.Csr.Index.euen), new EuenBundle)
+  val euen = viewUInt(csr(spec.Csr.Index.euen), new EuenBundle)
 
   // ECFG 例外控制
-  val ecfg = viewUInt(csrRegs(spec.Csr.Index.ecfg), new EcfgBundle)
+  val ecfg = viewUInt(csr(spec.Csr.Index.ecfg), new EcfgBundle)
 
   // ESTAT
-  val estat = viewUInt(csrRegs(spec.Csr.Index.estat), new EstatBundle)
+  val estat = viewUInt(csr(spec.Csr.Index.estat), new EstatBundle)
 
   // ERA 例外返回地址: 触发例外指令的pc记录在此
-  val era = viewUInt(csrRegs(spec.Csr.Index.era), new EraBundle)
+  val era = viewUInt(csr(spec.Csr.Index.era), new EraBundle)
 
   // BADV 出错虚地址
-  val badv = viewUInt(csrRegs(spec.Csr.Index.badv), new BadvBundle)
+  val badv = viewUInt(csr(spec.Csr.Index.badv), new BadvBundle)
 
   // EENTRY 例外入口地址
-  val eentry = viewUInt(csrRegs(spec.Csr.Index.eentry), new EentryBundle)
+  val eentry = viewUInt(csr(spec.Csr.Index.eentry), new EentryBundle)
 
   // CPUID 处理器编号
-  val cpuid = viewUInt(csrRegs(spec.Csr.Index.cpuid), new CpuidBundle)
+  val cpuid = viewUInt(csr(spec.Csr.Index.cpuid), new CpuidBundle)
 
   // SAVE0-3 数据保存
   val saves = VecInit(spec.Csr.Index.save0, spec.Csr.Index.save1, spec.Csr.Index.save2, spec.Csr.Index.save3).map {
     idx =>
-      viewUInt(csrRegs(idx), new CsrSaveBundle)
+      viewUInt(csr(idx), new CsrSaveBundle)
   }
 
   // LLBCTL  LLBit控制
-  val llbctl = viewUInt(csrRegs(spec.Csr.Index.llbctl), new LlbctlBundle)
+  val llbctl = viewUInt(csr(spec.Csr.Index.llbctl), new LlbctlBundle)
 
   // TLBIDX  TLB索引
-  val tlbidx = viewUInt(csrRegs(spec.Csr.Index.tlbidx), new TlbidxBundle)
+  val tlbidx = viewUInt(csr(spec.Csr.Index.tlbidx), new TlbidxBundle)
 
   // TLBEHI  TLB表项高位
-  val tlbehi = viewUInt(csrRegs(spec.Csr.Index.tlbehi), new TlbehiBundle)
+  val tlbehi = viewUInt(csr(spec.Csr.Index.tlbehi), new TlbehiBundle)
 
   // TLBELO 0-1  TLB表项低位
-  val tlbelo0 = viewUInt(csrRegs(spec.Csr.Index.tlbelo0), new TlbeloBundle)
+  val tlbelo0 = viewUInt(csr(spec.Csr.Index.tlbelo0), new TlbeloBundle)
 
-  val tlbelo1 = viewUInt(csrRegs(spec.Csr.Index.tlbelo1), new TlbeloBundle)
+  val tlbelo1 = viewUInt(csr(spec.Csr.Index.tlbelo1), new TlbeloBundle)
 
   // ASID 地址空间标识符
-  val asid = viewUInt(csrRegs(spec.Csr.Index.asid), new AsidBundle)
+  val asid = viewUInt(csr(spec.Csr.Index.asid), new AsidBundle)
 
   // PGDL 低半地址空间全局目录基址
-  val pgdl = viewUInt(csrRegs(spec.Csr.Index.pgdl), new PgdlBundle)
+  val pgdl = viewUInt(csr(spec.Csr.Index.pgdl), new PgdlBundle)
 
   // PGDH 高半地址空间全局目录基址
-  val pgdh = viewUInt(csrRegs(spec.Csr.Index.pgdh), new PgdhBundle)
+  val pgdh = viewUInt(csr(spec.Csr.Index.pgdh), new PgdhBundle)
 
   // PGD 全局地址空间全局目录基址
-  val pgd = viewUInt(csrRegs(spec.Csr.Index.pgd), new PgdBundle)
+  val pgd = viewUInt(csr(spec.Csr.Index.pgd), new PgdBundle)
 
   // TLBRENTRY  TLB重填例外入口地址
-  val tlbrentry = viewUInt(csrRegs(spec.Csr.Index.tlbrentry), new TlbrentryBundle)
+  val tlbrentry = viewUInt(csr(spec.Csr.Index.tlbrentry), new TlbrentryBundle)
 
   // DMW 0-1 直接映射配置窗口
-  val dmw0 = viewUInt(csrRegs(spec.Csr.Index.dmw0), new DmwBundle)
+  val dmw0 = viewUInt(csr(spec.Csr.Index.dmw0), new DmwBundle)
 
-  val dmw1 = viewUInt(csrRegs(spec.Csr.Index.dmw1), new DmwBundle)
+  val dmw1 = viewUInt(csr(spec.Csr.Index.dmw1), new DmwBundle)
 
   // TID 定时器编号
-  val tid = viewUInt(csrRegs(spec.Csr.Index.tid), new TidBundle)
+  val tid = viewUInt(csr(spec.Csr.Index.tid), new TidBundle)
 
   // TCFG 定时器配置
-  val tcfg = viewUInt(csrRegs(spec.Csr.Index.tcfg), new TcfgBundle)
+  val tcfg = viewUInt(csr(spec.Csr.Index.tcfg), new TcfgBundle)
 
   // TVAL 定时器数值
-  val tval = viewUInt(csrRegs(spec.Csr.Index.tval), new TvalBundle)
+  val tval = viewUInt(csr(spec.Csr.Index.tval), new TvalBundle)
 
   // TICLR 定时器中断清除
-  val ticlr = viewUInt(csrRegs(spec.Csr.Index.ticlr), new TiclrBundle)
+  val ticlr = viewUInt(csr(spec.Csr.Index.ticlr), new TiclrBundle)
 
   // read
   io.readPorts.foreach { readPort =>
     readPort.data := zeroWord
     when(readPort.en) {
-      readPort.data := csrRegs(readPort.addr)
+      readPort.data := csr(readPort.addr)
       when(readPort.addr === spec.Csr.Index.pgd) {
         readPort.data := Mux(
           badv.out.vaddr(31),
-          csrRegs(spec.Csr.Index.pgdh),
-          csrRegs(spec.Csr.Index.pgdl)
+          csr(spec.Csr.Index.pgdh),
+          csr(spec.Csr.Index.pgdl)
         )
       }
     }
@@ -147,7 +147,7 @@ class Csr(
     }
   }
 
-  // 软件写csrRegs
+  // 软件写csr
   // 保留域断断续续的样子真是可爱捏
   io.writePorts.foreach { writePort =>
     when(writePort.en) {

diff --git a/src/src/control/Cu.scala b/src/src/control/Cu.scala
@@ -11,9 +11,8 @@ import spec.{Csr, ExeInst, Param}
 
 // Note. Exception只从第0个提交
 class Cu(
-  ctrlControlNum: Int = Param.ctrlControlNum,
-  writeNum:       Int = Param.csrRegsWriteNum,
-  commitNum:      Int = Param.commitNum)
+  writeNum:  Int = Param.csrWriteNum,
+  commitNum: Int = Param.commitNum)
     extends Module {
   val io = IO(new Bundle {
 
@@ -48,9 +47,6 @@ class Cu(
     // -> `MemReqStage`
     val isAfterMemReqFlush = Output(Bool())
 
-    // <- `Rob`
-    // val robInstValids = Input(Vec(Param.Width.Rob._length, Bool()))
-
     // <- Out
     val hardWareInetrrupt = Input(UInt(8.W))
 
@@ -67,10 +63,6 @@ class Cu(
   io.csrMessage := CuToCsrNdPort.default
   io.newPc      := PcSetPort.default
 
-  // val linesHasException = WireDefault(VecInit(io.instInfoPorts.map { instInfo =>
-  //   (instInfo.exceptionPos =/= ExceptionPos.none) && instInfo.isValid
-  // }))
-  // val hasException = WireDefault(linesHasException.reduce(_ || _))
   val hasException = WireDefault(io.instInfoPorts(0).exceptionPos =/= ExceptionPos.none) && io.instInfoPorts(0).isValid
 
   /** stable counter
@@ -109,8 +101,6 @@ class Cu(
   io.csrMessage.exceptionFlush := hasException
   // Attention: 由于encoder在全零的情况下会选择idx最高的那个，
   // 使用时仍需判断是否有exception
-  // val selectLineNum      = PriorityEncoder(linesHasException)
-  // val selectInstInfo     = WireDefault(io.instInfoPorts(selectLineNum))
   val selectInstInfo     = WireDefault(io.instInfoPorts(0))
   val selectException    = WireDefault(selectInstInfo.exceptionRecord)
   val selectExceptionPos = WireDefault(selectInstInfo.exceptionPos)
@@ -212,25 +202,19 @@ class Cu(
   /** Flush & jump
     */
 
-  val exceptionFlush = WireDefault(hasException)
-
   val ertnFlush = WireDefault(
     io.instInfoPorts.map { instInfo => instInfo.exeOp === ExeInst.Op.ertn && instInfo.isValid }.reduce(_ || _)
   )
 
   // Handle after memory request exception valid
   io.isAfterMemReqFlush := io.isExceptionValidVec.asUInt.orR
 
-  // io.exceptionFlush := RegNext(exceptionFlush, false.B)
-  // val branchSetEnable = WireDefault(io.jumpPc.en && io.robInstValids(io.jumpPc.robId))
-  // io.branchFlushInfo.en    := RegNext(branchSetEnable)
-  // io.branchFlushInfo.robId := RegNext(io.jumpPc.robId)
   io.csrMessage.ertnFlush := ertnFlush
-  io.frontendFlush        := RegNext(exceptionFlush || io.branchExe.en, false.B)
-  io.backendFlush         := RegNext(exceptionFlush || io.branchCommit, false.B)
+  io.frontendFlush        := RegNext(hasException || io.branchExe.en, false.B)
+  io.backendFlush         := RegNext(hasException || io.branchCommit, false.B)
 
   // select new pc
-  when(exceptionFlush) {
+  when(hasException) {
     io.newPc.en     := true.B
     io.newPc.isIdle := false.B
     when(isTlbRefillException) {
@@ -248,12 +232,9 @@ class Cu(
     io.instInfoPorts(0).csrWritePort.data(1, 0).orR
 
   io.difftest match {
-    case Some(dt) => {
-      dt.cmt_ertn := RegNext(ertnFlush)
-      dt.cmt_excp_flush := RegNext(
-        exceptionFlush
-      )
-    }
+    case Some(dt) =>
+      dt.cmt_ertn       := RegNext(ertnFlush)
+      dt.cmt_excp_flush := RegNext(hasException)
     case _ =>
   }
 }
diff --git a/src/src/control/bundles/CsrValuePort.scala b/src/src/control/bundles/CsrValuePort.scala
@@ -1,7 +1,7 @@
 package control.bundles
 
 import chisel3._
-import control.csrRegsBundles._
+import control.csrBundles._
 
 class CsrValuePort extends Bundle {
   val crmd      = new CrmdBundle

diff --git a/src/src/control/csrRegsBundles/AsidBundle.scala b/src/src/control/csrRegsBundles/AsidBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 

diff --git a/src/src/control/csrRegsBundles/BadvBundle.scala b/src/src/control/csrRegsBundles/BadvBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 import spec._

diff --git a/src/src/control/csrRegsBundles/CpuidBundle.scala b/src/src/control/csrRegsBundles/CpuidBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._