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fix: small optimization #191

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Merged
rewired-gh merged 1 commit into from
Jul 3, 2023
Merged

fix: small optimization #191

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18 changes: 9 additions & 9 deletions src/src/pipeline/memory/MemReqStage.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -198,19 +198,19 @@ class MemReqStage
out.isRead := false.B
out.dataMask := storeOut.bits.mask

peer.dCacheReq.client.rw := ReadWriteSel.write
peer.dCacheReq.client.addr := storeOut.bits.addr
peer.dCacheReq.client.mask := storeOut.bits.mask
peer.dCacheReq.client.write.data := storeOut.bits.data
peer.uncachedReq.client.rw := ReadWriteSel.write
peer.uncachedReq.client.addr := storeOut.bits.addr
peer.uncachedReq.client.mask := storeOut.bits.mask
peer.uncachedReq.client.write.data := storeOut.bits.data

isComputed := false.B

// Whether can submit memory request instantly
when(peer.commitStore.ready) {
peer.dCacheReq.client.rw := ReadWriteSel.write
peer.dCacheReq.client.addr := storeOut.bits.addr
peer.dCacheReq.client.mask := storeOut.bits.mask
peer.dCacheReq.client.write.data := storeOut.bits.data
peer.uncachedReq.client.rw := ReadWriteSel.write
peer.uncachedReq.client.addr := storeOut.bits.addr
peer.uncachedReq.client.mask := storeOut.bits.mask
peer.uncachedReq.client.write.data := storeOut.bits.data

storeOut.ready := true.B
resultOutReg.valid := true.B

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