fix: false cache write-back of cache maintenance

src/src/memory/DCache.scala

@@ -428,7 +428,8 @@ class DCache(
               } else {
                 refillSetIndex := 0.U
               }
-              isNeedWbReg := true.B
+              isNeedWbReg           := true.B
+              isWriteBackReqSentReg := false.B
 
               // Save data for later use
               lastReg.dataLine := toDataLine(dataLines(refillSetIndex))
@@ -457,20 +458,25 @@ class DCache(
 
       // Maintenance
       setCountDownReg := (Param.Count.DCache.setLen - 1).U
-
       when(io.maintenancePort.client.control.isL1Valid) {
-        isNeedWbReg           := true.B
-        isWriteBackReqSentReg := false.B
-
         when(io.maintenancePort.client.control.isInit) {
+          isNeedWbReg           := true.B
+          isWriteBackReqSentReg := false.B
+
           // Next Stage: Maintenance for all sets (no write-back)
           nextState := State.maintenanceInit
         }
         when(io.maintenancePort.client.control.isCoherentByIndex) {
+          isNeedWbReg           := true.B
+          isWriteBackReqSentReg := false.B
+
           // Next Stage: Maintenance for all sets
           nextState := State.maintenanceAll
         }
         when(io.maintenancePort.client.control.isCoherentByHit) {
+          isNeedWbReg           := true.B
+          isWriteBackReqSentReg := false.B
+
           // Next Stage: Maintenance only for hit
           nextState := State.maintenanceHit
         }

src/src/spec/Param.scala

@@ -110,7 +110,7 @@ object Param {
     }
 
     object DCache {
-      val setLen      = 2 // Also the number of RAMs for data; TODO: Choose an optimal value
+      val setLen      = 1 // Also the number of RAMs for data; TODO: Choose an optimal value
       val dataPerLine = 16 // TODO: One data line is 64 bytes
       val sizePerRam  = math.pow(2, Width.DCache._addr).toInt
     }