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fix:branch predict update bug #258

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NotTheEndOfTheWorld merged 2 commits into from
Jul 18, 2023
Merged

fix:branch predict update bug #258

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25f2ab8
fix:bug
NotTheEndOfTheWorld Jul 18, 2023
0a86ca1
change param
NotTheEndOfTheWorld Jul 18, 2023
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138 changes: 69 additions & 69 deletions src/src/frontend/bpu/TagePredictor.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -12,16 +12,16 @@ import frontend.bpu.utils.Lfsr
// TAGE predictor
// This is the main predictor
class TagePredictor(
tagComponentNum: Int = Param.BPU.TagePredictor.tagComponentNum,
tagComponentTagWidth: Int = Param.BPU.TagePredictor.tagComponentTagWidth,
ghrDepth: Int = Param.BPU.TagePredictor.ghrLength,
historyLengths: Seq[Int] = Param.BPU.TagePredictor.componentHistoryLength,
phtDepths: Seq[Int] = Param.BPU.TagePredictor.componentTableDepth,
componentCtrWidth: Seq[Int] = Param.BPU.TagePredictor.componentCtrWidth,
componentUsefulWidth: Seq[Int] = Param.BPU.TagePredictor.componentUsefulWidth,
entryNum: Int = Param.BPU.RAS.entryNum,
addr: Int = spec.Width.Mem._addr)
extends Module {
tagComponentNum: Int = Param.BPU.TagePredictor.tagComponentNum,
tagComponentTagWidth: Int = Param.BPU.TagePredictor.tagComponentTagWidth,
ghrDepth: Int = Param.BPU.TagePredictor.ghrLength,
historyLengths: Seq[Int] = Param.BPU.TagePredictor.componentHistoryLength,
phtDepths: Seq[Int] = Param.BPU.TagePredictor.componentTableDepth,
componentCtrWidth: Seq[Int] = Param.BPU.TagePredictor.componentCtrWidth,
componentUsefulWidth: Seq[Int] = Param.BPU.TagePredictor.componentUsefulWidth,
entryNum: Int = Param.BPU.RAS.entryNum,
addr: Int = spec.Width.Mem._addr)
extends Module {
val addrWidth = log2Ceil(addr)
val pointerWidth = log2Ceil(entryNum)
val tagComPtrWidth = log2Ceil(tagComponentNum + 1)
Expand All @@ -37,7 +37,7 @@ class TagePredictor(
val updateInfoPort = Input(new TagePredictorUpdateInfoPort)

// TODO PMU
// val perfTagHitCounters = Output(Vec(32, UInt((tagComponentNum + 1).W)))
// val perfTagHitCounters = Output(Vec(32, UInt((tagComponentNum + 1).W)))

})

Expand Down Expand Up @@ -82,9 +82,9 @@ class TagePredictor(
val isBaseUpdateCtr = WireDefault(false.B)
val isUpdateValid = WireDefault(false.B)
val globalHistoryUpdateReg = RegInit(false.B)
val updatePredictCorrect = WireDefault(0.U(tagComponentNum.W))
val updateBranchTaken = WireDefault(0.U(tagComponentNum.W))
val updateIsConditional = WireDefault(0.U(tagComponentNum.W))
val updatePredictCorrect = WireDefault(false.B)
val updateBranchTaken = WireDefault(false.B)
val updateIsConditional = WireDefault(false.B)
val updateNewEntryFlag = WireDefault(false.B) // Indicates the provider is new
val updateProviderId = WireDefault(0.U(tagComPtrWidth.W))
val updateALtProviderId = WireDefault(0.U(tagComPtrWidth.W))
Expand Down Expand Up @@ -139,41 +139,41 @@ class TagePredictor(

// Tagged Predictor Generate
val taggedPreditors = Seq.range(0, tagComponentNum).map { providerId =>
{
val taggedPreditor = Module(
new TaggedPreditor(
ghrLength = historyLengths(providerId + 1),
phtDepth = phtDepths(providerId + 1),
phtUsefulWidth = componentUsefulWidth(providerId + 1),
phtCtrWidth = componentCtrWidth(providerId + 1)
)
{
val taggedPreditor = Module(
new TaggedPreditor(
ghrLength = historyLengths(providerId + 1),
phtDepth = phtDepths(providerId + 1),
phtUsefulWidth = componentUsefulWidth(providerId + 1),
phtCtrWidth = componentCtrWidth(providerId + 1)
)
// Query
taggedPreditor.io.isGlobalHistoryUpdate := isUpdateValid
taggedPreditor.io.globalHistory := ghr(historyLengths(providerId + 1), 0)
taggedPreditor.io.pc := io.pc
tagUsefuls(providerId) := taggedPreditor.io.usefulBits
tagCtrs(providerId) := taggedPreditor.io.ctrBits
tagQueryTags(providerId) := taggedPreditor.io.queryTag
tagOriginTags(providerId) := taggedPreditor.io.hitIndex
tagTaken(providerId) := taggedPreditor.io.taken
tagHit(providerId) := taggedPreditor.io.tagHit

// update
taggedPreditor.io.updatePc := io.updatePc
taggedPreditor.io.updateValid := (isUpdateValid & updateIsConditional)
taggedPreditor.io.incUseful := tagUpdateIncUseful(providerId)
taggedPreditor.io.updateUseful := tagUpdateUseful(providerId)
taggedPreditor.io.updateUsefulBits := updateMetaBundle.tagPredictorUsefulBits(providerId)
taggedPreditor.io.updateCtr := tagUpdateCtr.asBools(providerId)
taggedPreditor.io.incCtr := updateBranchTaken.asBools(providerId)
taggedPreditor.io.updateCtrBits := updateMetaBundle.providerCtrBits(providerId)
taggedPreditor.io.reallocEntry := tagUpdateReallocEntry(providerId)
taggedPreditor.io.updateTag := tagUpdateNewTags(providerId)
taggedPreditor.io.updateIndex := updateMetaBundle.tagPredictorHitIndex(providerId)

taggedPreditor
}
)
// Query
taggedPreditor.io.isGlobalHistoryUpdate := isUpdateValid
taggedPreditor.io.globalHistory := ghr(historyLengths(providerId + 1), 0)
taggedPreditor.io.pc := io.pc
tagUsefuls(providerId) := taggedPreditor.io.usefulBits
tagCtrs(providerId) := taggedPreditor.io.ctrBits
tagQueryTags(providerId) := taggedPreditor.io.queryTag
tagOriginTags(providerId) := taggedPreditor.io.hitIndex
tagTaken(providerId) := taggedPreditor.io.taken
tagHit(providerId) := taggedPreditor.io.tagHit

// update
taggedPreditor.io.updatePc := io.updatePc
taggedPreditor.io.updateValid := isUpdateValid && updateIsConditional
taggedPreditor.io.incUseful := tagUpdateIncUseful(providerId)
taggedPreditor.io.updateUseful := tagUpdateUseful(providerId)
taggedPreditor.io.updateUsefulBits := updateMetaBundle.tagPredictorUsefulBits(providerId)
taggedPreditor.io.updateCtr := tagUpdateCtr.asBools(providerId)
taggedPreditor.io.incCtr := updateBranchTaken
taggedPreditor.io.updateCtrBits := updateMetaBundle.providerCtrBits(providerId)
taggedPreditor.io.reallocEntry := tagUpdateReallocEntry(providerId)
taggedPreditor.io.updateTag := tagUpdateNewTags(providerId)
taggedPreditor.io.updateIndex := updateMetaBundle.tagPredictorHitIndex(providerId)

taggedPreditor
}
}

queryIsUseful := (takens(predPredictionId) =/= takens(altPredPredctionId))
Expand Down Expand Up @@ -208,7 +208,7 @@ class TagePredictor(

// Output logic
io.predictValid := true.B
// takens := Cat(tagTaken, baseTaken)
// takens := Cat(tagTaken, baseTaken)
Seq.range(1, tagComponentNum + 1).foreach { i =>
takens(i) := tagTaken(i - 1)
}
Expand Down Expand Up @@ -239,10 +239,10 @@ class TagePredictor(
// skip ctrBitsVec(0)
queryMetaBundle.providerCtrBits(i + 1) := tagCtrs(i)
)
// queryMetaPort.providerCtrBits.drop(1).zip(tagCtrs).foreach {
// case (dst, src) =>
// dst := src
// }
// queryMetaPort.providerCtrBits.drop(1).zip(tagCtrs).foreach {
// case (dst, src) =>
// dst := src
// }
io.bpuMetaPort := BpuFtqMetaNdPort.default
io.bpuMetaPort.bpuMeta := queryMetaBundle

Expand All @@ -253,19 +253,19 @@ class TagePredictor(
// USE_ALT_ON_NA
updateNewEntryFlag := (updateMetaBundle.providerCtrBits(updateProviderId - 1.U) === 3.U(3.W) ||
updateMetaBundle.providerCtrBits(updateProviderId - 1.U) === 4.U(3.W) &&
updateProviderId =/= 0.U)
updateProviderId =/= 0.U)
when(
isUpdateValid & updateNewEntryFlag &
updateMetaBundle.useful & ~io.updateInfoPort.predictCorrect
isUpdateValid && updateNewEntryFlag &&
updateMetaBundle.useful && !io.updateInfoPort.predictCorrect
) {
useAltOnNaCounterTablesReg(updatePc(4, 2)) := Mux(
useALtOnNaCounter === 15.U(4.W),
15.U(4.W),
useALtOnNaCounter + 1.U
)
}.elsewhen(
isUpdateValid & updateNewEntryFlag &
updateMetaBundle.useful & io.updateInfoPort.predictCorrect
isUpdateValid && updateNewEntryFlag &&
updateMetaBundle.useful && io.updateInfoPort.predictCorrect
) {
useAltOnNaCounterTablesReg(updatePc(4, 2)) := Mux(useALtOnNaCounter === 0.U(4.W), 0.U(4.W), useALtOnNaCounter - 1.U)
}
Expand Down Expand Up @@ -323,13 +323,13 @@ class TagePredictor(
// Fill update structs
// update ctr Policy
// update provider
when(updateIsConditional.orR & isUpdateValid) {
when(updateIsConditional && isUpdateValid) {
updateCtr(updateProviderId) := true.B
}

// update altProvider if new entry
when(
updateNewEntryFlag && updateIsConditional.orR &&
updateNewEntryFlag && updateIsConditional &&
!io.updateInfoPort.predictCorrect && isUpdateValid
) {
updateCtr(updateALtProviderId) := true.B
Expand All @@ -338,13 +338,13 @@ class TagePredictor(
// tag update policy

// Default 0
// val tagUpdateUseful = WireDefault(0.U((tagComponentNum + 1).W))
// val tagUpdateIncUseful = WireDefault(0.U((tagComponentNum + 1).W))
// val tagUpdateReallocEntry = WireDefault(0.U((tagComponentNum + 1).W))
// val tagUpdateUseful = WireDefault(0.U((tagComponentNum + 1).W))
// val tagUpdateIncUseful = WireDefault(0.U((tagComponentNum + 1).W))
// val tagUpdateReallocEntry = WireDefault(0.U((tagComponentNum + 1).W))

// Only update on conditional branches
when(updateIsConditional.xorR & isUpdateValid) {
when(updatePredictCorrect.xorR) {
when(updateIsConditional & isUpdateValid) {
when(updatePredictCorrect) {
// if useful,update useful bits
tagUpdateUseful(updateProviderId - 1.U) := updateMetaBundle.useful
// Increase if correct, else decrease
Expand Down Expand Up @@ -377,10 +377,10 @@ class TagePredictor(
)
}

// // counter
// Seq.range(0, tagComponentNum + 1).foreach { i =>
// io.perfTagHitCounters(i) := io.perfTagHitCounters(i) + Cat(0.U(31.W), (i.U === predPredictionId))
// }
// // counter
// Seq.range(0, tagComponentNum + 1).foreach { i =>
// io.perfTagHitCounters(i) := io.perfTagHitCounters(i) + Cat(0.U(31.W), (i.U === predPredictionId))
// }

// todo debug

Expand Down
44 changes: 0 additions & 44 deletions src/src/spec/Param.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -186,8 +186,6 @@ object Param {
val entryNum = 32
}

val decodeWidth = 1 // 2 to do
val commitWidth = 1 // 2 to do
object BranchType {
var count = 0
private def next = {
Expand All @@ -203,48 +201,6 @@ object Param {
}
}

// object BPU {
// val fetchWidth = 4
// val ftqSize = 8

// object TagePredictor {
// val ghrLength = 1400
// val tagComponentNum = 15
// val tagComponentTagWidth = 12
// // ComponentTableDepth
// // length = tagComponentNum +1
// val componentTableDepth =
// Seq(16384, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024)
// val componentCtrWidth = Seq(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3)
// val componentUsefulWidth = Seq(0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3)
// val componentHistoryLength = Seq(0, 6, 10, 18, 25, 35, 55, 69, 105, 155, 230, 354, 479, 642, 1012, 1347)

// }

// object FTB {
// val nset = 1024
// val nway = 4
// }

// object RAS {
// val entryNum = 32
// }

// val decodeWidth = 1 // 2 to do
// val commitWidth = 1 // 2 to do
// object BranchType {
// var count = 0
// private def next = {
// count += 1
// count.U
// }
// val cond = 0.U
// val call = next
// val ret = next
// val uncond = next
// }
// }

object SimpleFetchStageState extends ChiselEnum {
val idle, requestInst, waitInst = Value
}
Expand Down