refactor: rename file

src/src/CoreCpuTop.scala

@@ -103,8 +103,8 @@ class CoreCpuTop extends Module {
   val iCache           = Module(new ICache)
   val frontend         = Module(new Frontend)
   val instQueue        = Module(new MultiInstQueue)
-  val renameStage      = Module(new NewRenameStage)
-  val dispatchStage    = Module(new NewDispatchStage)
+  val renameStage      = Module(new RenameStage)
+  val dispatchStage    = Module(new DispatchStage)
   val exeForMemStage   = Module(new ExeForMemStage)
   val exePassWbStage_1 = Module(new ExePassWbStage(supportBranchCsr = true))
   val exePassWbStage_2 = Module(new ExePassWbStage(supportBranchCsr = false))

src/src/pipeline/dispatch/NewDispatchStage.scala → src/src/pipeline/dispatch/DispatchStage.scala

@@ -22,7 +22,7 @@ import pmu.bundles.PmuDispatchBundle
 //   def default = 0.U.asTypeOf(new DispatchNdPort)
 // }
 
-class NewDispatchPeerPort extends Bundle {
+class DispatchPeerPort extends Bundle {
 
   val plv = Input(UInt(2.W))
 
@@ -33,15 +33,15 @@ class NewDispatchPeerPort extends Bundle {
   val pmu_dispatchInfos = if (Param.usePmu) Some(Output(Vec(Param.pipelineNum, new PmuDispatchBundle))) else None
 }
 
-class NewDispatchStage(
+class DispatchStage(
   issueNum:       Int = Param.issueInstInfoMaxNum,
   pipelineNum:    Int = Param.pipelineNum,
   outQueueLength: Int = Param.dispatchOutQueueLength)
     extends MultiBaseStageWOSaveIn(
       new ReservationStationBundle,
       new ExeNdPort,
       ReservationStationBundle.default,
-      Some(new NewDispatchPeerPort),
+      Some(new DispatchPeerPort),
       issueNum,
       pipelineNum,
       outQueueLength,

src/src/pipeline/dispatch/NewRenameStage.scala → src/src/pipeline/dispatch/RenameStage.scala

@@ -31,7 +31,7 @@ object RegReadNdPort {
   )
 }
 
-class NewRenamePeerPort(
+class RenamePeerPort(
   issueNum:    Int = Param.issueInstInfoMaxNum,
   pipelineNum: Int = Param.pipelineNum)
     extends Bundle {
@@ -44,15 +44,15 @@ class NewRenamePeerPort(
   val writebacks = Input(Vec(pipelineNum, new InstWbNdPort))
 }
 
-class NewRenameStage(
+class RenameStage(
   issueNum:          Int = Param.issueInstInfoMaxNum,
   pipelineNum:       Int = Param.pipelineNum,
   reservationLength: Int = Param.Width.ReservationStation._length)
     extends Module {
   val io = IO(new Bundle {
     val ins     = Vec(issueNum, Flipped(Decoupled(new FetchInstDecodeNdPort)))
     val outs    = Vec(issueNum, Decoupled(new ReservationStationBundle))
-    val peer    = Some(new NewRenamePeerPort)
+    val peer    = Some(new RenamePeerPort)
     val isFlush = Input(Bool())
   })
   protected val selectedIns: Vec[FetchInstDecodeNdPort] = Wire(

src/src/pipeline/execution/Alu.scala

@@ -148,7 +148,7 @@ class Alu extends Module {
     ).contains(io.aluInst.op)
   )
 
-  val divStage = Module(new NewDiv)
+  val divStage = Module(new Div)
 
   val divisorValid = WireDefault(rop =/= 0.U)
 

src/src/pipeline/execution/NewDiv.scala → src/src/pipeline/execution/Div.scala

@@ -10,7 +10,7 @@ object DivState extends ChiselEnum {
 }
 
 // Attention : 如果运行时输入数据，输入无效
-class NewDiv extends Module {
+class Div extends Module {
 
   val io = IO(new Bundle {
     val divInst = Input(Valid(new MulDivInstNdPort))