Introduce speculative update global history

src/src/ComplexCoreCpuTop.scala

@@ -179,6 +179,8 @@ class ComplexCoreCpuTop extends Module {
     case (dst, src) =>
       dst := src
   }
+  frontend.io.commitFixBranch := false.B
+  frontend.io.commitFixId     := 0.U
 
   // Instruction queue
   instQueue.io.enqueuePort <> frontend.io.instDequeuePort

src/src/SimpleCoreCpuTop.scala

@@ -1,5 +1,4 @@
 import pipeline.simple.MainExeStage
-import pipeline.simple.id.IssueStage
 import axi.Axi3x1Crossbar
 import axi.bundles.AxiMasterInterface
 import chisel3._
@@ -189,8 +188,13 @@ class SimpleCoreCpuTop extends Module {
 
   // TODO: Connect frontend
   frontend.io.exeFtqPort.queryPcBundle <> issueQueue.io.queryPcPort
-  frontend.io.exeFtqPort.commitBundle  := mainExeStage.io.peer.get.feedbackFtq
-  frontend.io.commitFtqTrainPort       := addrTransStage.io.peer.get.commitFtqPort
+  frontend.io.exeFtqPort.feedBack      := mainExeStage.io.peer.get.feedbackFtq
+  val commitFtqPort =
+    if (isNoPrivilege) mainExeStage.io.peer.get.commitFtqPort
+    else addrTransStage.io.peer.get.commitFtqPort
+  frontend.io.commitFtqTrainPort := commitFtqPort
+  frontend.io.commitFixBranch    := false.B
+  frontend.io.commitFixId        := 0.U
   connectVec(frontend.io.commitBitMask, cu.io.commitBitMask)
 
   // Instruction queue

src/src/frontend/FetchTargetQueue.scala

@@ -17,10 +17,11 @@ class FetchTargetQueue(
 
   val io = IO(new Bundle {
     // <-> Frontend flush control
-    val backendFlush      = Input(Bool())
-    val backendFlushFtqId = Input(UInt(ptrWidth.W))
-    val instFetchFlush    = Input(Bool())
-    val instFetchFtqId    = Input(UInt(ptrWidth.W))
+    val backendFlush          = Input(Bool())
+    val backendFlushFtqId     = Input(UInt(ptrWidth.W))
+    val preDecoderFlush       = Input(Bool())
+    val preDecoderFtqId       = Input(UInt(ptrWidth.W))
+    val preDecoderBranchTaken = Input(Bool())
 
     // <-> BPU
     val bpuFtqPort = new BpuFtqPort
@@ -116,9 +117,9 @@ class FetchTargetQueue(
   }
 
   // if IF predecoder found a redirect
-  when(io.instFetchFlush) {
-    nextIfPtr := io.instFetchFtqId + 1.U
-    bpuPtr    := io.instFetchFtqId + 1.U
+  when(io.preDecoderFlush) {
+    nextIfPtr := io.preDecoderFtqId + 1.U
+    bpuPtr    := io.preDecoderFtqId + 1.U
   }
   // if backend redirect triggered,back to the next block of the redirect block
   // backend may continue to commit older block (flush before exeStage inst;commit after exeStage inst)
@@ -187,7 +188,16 @@ class FetchTargetQueue(
   io.bpuFtqPort.ftqFull := queueFull
 
   // training meta to BPU
-  io.bpuFtqPort.ftqBpuTrainMeta := FtqBpuMetaPort.default
+  io.bpuFtqPort.ftqBpuTrainMeta                                               := FtqBpuMetaPort.default
+  io.bpuFtqPort.ftqBpuTrainMeta.ghrUpdateSignalBundle.exeFixBundle            := io.exeFtqPort.feedBack.fixGhrBundle
+  io.bpuFtqPort.ftqBpuTrainMeta.ghrUpdateSignalBundle.isPredecoderFixGhr      := io.preDecoderFlush
+  io.bpuFtqPort.ftqBpuTrainMeta.ghrUpdateSignalBundle.isPredecoderBranchTaken := io.preDecoderBranchTaken
+  io.bpuFtqPort.ftqBpuTrainMeta.tageGhrInfo :=
+    Mux(
+      io.backendFlush,
+      ftqBpuMetaRegs(io.backendFlushFtqId).tageQueryMeta.tageGhrInfo,
+      ftqBpuMetaRegs(io.preDecoderFtqId).tageQueryMeta.tageGhrInfo
+    )
 //  when(
 //    io.cuCommitFtqPort.blockBitmask(0) & io.cuCommitFtqPort.meta.isBranch
 //  ) {
@@ -204,7 +214,7 @@ class FetchTargetQueue(
 
   io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.startPc         := ftqVecReg(commitFtqId).startPc
   io.bpuFtqPort.ftqBpuTrainMeta.isCrossCacheline                 := ftqVecReg(commitFtqId).isCrossCacheline
-  io.bpuFtqPort.ftqBpuTrainMeta.tageOriginMeta                         := ftqBpuMetaRegs(commitFtqId).tageQueryMeta
+  io.bpuFtqPort.ftqBpuTrainMeta.tageOriginMeta                   := ftqBpuMetaRegs(commitFtqId).tageQueryMeta
   io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.jumpTargetAddr  := ftqBranchMetaRegs(commitFtqId).jumpTargetAddr
   io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.fallThroughAddr := ftqBranchMetaRegs(commitFtqId).fallThroughAddr
 
@@ -231,6 +241,7 @@ class FetchTargetQueue(
     io.bpuFtqPort.bpuQueryMeta,
     BpuFtqMetaNdPort.default
   )
+  bpuMetaWriteEntry.tageQueryMeta.tageGhrInfo := io.bpuFtqPort.bpuQueryMeta.tageQueryMeta.tageGhrInfo
 //  when(io.bpuFtqPort.ftqP1.isValid & ~mainBpuRedirectDelay) {
 //    bpuMetaWriteValid             := true.B
 //    bpuMetaWritePtr               := bpuPtr - 1.U
@@ -259,16 +270,19 @@ class FetchTargetQueue(
   when(bpuMetaWriteValid) {
     ftqBpuMetaRegs(bpuMetaWritePtr) := bpuMetaWriteEntry
   }
+  when(io.preDecoderFlush) {
+    ftqBpuMetaRegs(io.preDecoderFtqId).tageQueryMeta.tageGhrInfo := io.bpuFtqPort.bpuQueryMeta.tageQueryMeta.tageGhrInfo
+  }
   // update pc from backend
-  when(io.exeFtqPort.commitBundle.ftqMetaUpdateValid) {
-    val ftqUpdateMetaId = WireDefault(io.exeFtqPort.commitBundle.ftqUpdateMetaId)
+  when(io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateValid) {
+    val ftqUpdateMetaId = WireDefault(io.exeFtqPort.feedBack.commitBundle.ftqUpdateMetaId)
     ftqBranchMetaRegs(
       ftqUpdateMetaId
-    ).jumpTargetAddr := io.exeFtqPort.commitBundle.ftqMetaUpdateJumpTarget
+    ).jumpTargetAddr := io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateJumpTarget
     ftqBranchMetaRegs(
       ftqUpdateMetaId
-    ).fallThroughAddr                           := io.exeFtqPort.commitBundle.ftqMetaUpdateFallThrough
-    ftqBranchMetaRegs(ftqUpdateMetaId).ftbDirty := io.exeFtqPort.commitBundle.ftqMetaUpdateFtbDirty
+    ).fallThroughAddr                           := io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFallThrough
+    ftqBranchMetaRegs(ftqUpdateMetaId).ftbDirty := io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFtbDirty
   }
 
 }

src/src/frontend/Frontend.scala

@@ -23,6 +23,8 @@ class Frontend extends Module {
     // ftq <-> cu
     val commitFtqTrainPort = Input(new CommitFtqTrainNdPort)
     val commitBitMask      = Input(Vec(Param.commitNum, Bool()))
+    val commitFixBranch    = Input(Bool())
+    val commitFixId        = Input(UInt(Param.BPU.ftqPtrWidth.W))
 
     // instFetch <-> ICache
     val accessPort = Flipped(new ICacheAccessPort)
@@ -66,10 +68,11 @@ class Frontend extends Module {
   // fetch Target Pc queue;
   // stage 1
   // act as a fetch buffer
-  ftq.io.backendFlush      := io.isFlush
-  ftq.io.backendFlushFtqId := io.ftqFlushId
-  ftq.io.instFetchFlush    := instFetch.io.preDecodeRedirectPort.predecodeRedirect // TODO add predecoder stage
-  ftq.io.instFetchFtqId    := instFetch.io.preDecodeRedirectPort.redirectFtqId
+  ftq.io.backendFlush          := io.isFlush
+  ftq.io.backendFlushFtqId     := io.ftqFlushId
+  ftq.io.preDecoderFlush       := instFetch.io.preDecodeRedirectPort.predecodeRedirect // TODO add predecoder stage
+  ftq.io.preDecoderFtqId       := instFetch.io.preDecodeRedirectPort.redirectFtqId
+  ftq.io.preDecoderBranchTaken := instFetch.io.preDecodeRedirectPort.predecoderBranch
   instFetch.io.preDecodeRedirectPort.commitRasPort := ftq.io.ftqRasPort
   ftq.io.commitFtqTrainPort                        := io.commitFtqTrainPort
   ftq.io.exeFtqPort                                <> io.exeFtqPort

src/src/frontend/bpu/BPU.scala

@@ -5,8 +5,8 @@ import chisel3.util._
 import frontend.bpu.bundles._
 import frontend.bpu.components.Bundles.{FtbEntryNdPort, TageMetaPort}
 import frontend.bpu.components.FTB
-import frontend.bundles.{BpuFtqPort, FtqBlockBundle}
-import spec.Param.BPU.BranchType
+import frontend.bundles.{BpuFtqPort, FtqBlockBundle, GhrUpdateSignalBundle}
+import spec.Param.BPU.{BranchType, GhrFixType}
 import spec._
 
 // BPU is the Branch Predicting Unit
@@ -144,7 +144,8 @@ class BPU(
       io.bpuRedirectPc.bits := ftbEntry.jumpTargetAddr
     }
     is(Param.BPU.BranchType.ret) {
-      // return inst is predict in pre decode Stage
+      // return inst is predict in preDecode Stage;
+      // when preDecode predict error,use ftb to predict
     }
   }
 
@@ -200,6 +201,28 @@ class BPU(
   ftbUpdateEntry.jumpTargetAddr   := io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.jumpTargetAddr
   ftbUpdateEntry.fallThroughAddr  := io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.fallThroughAddr
 
+  // global branch history update logic
+  val ghrFixBundle = Wire(new GhrFixNdBundle)
+  val ghrUpdateSignalBundle = WireDefault(
+    io.bpuFtqPort.ftqBpuTrainMeta.ghrUpdateSignalBundle
+  )
+  ghrFixBundle.isFixGhrValid    := ghrUpdateSignalBundle.isPredecoderFixGhr || io.backendFlush
+  ghrFixBundle.isFixBranchTaken := ghrUpdateSignalBundle.exeFixBundle.exeFixIsTaken
+//  ghrUpdateSignalBundle.isCommitFixGhr
+  ghrFixBundle.ghrFixType := Mux(
+    io.backendFlush && !ghrUpdateSignalBundle.exeFixBundle.isExeFixValid && !ghrUpdateSignalBundle.isPredecoderFixGhr,
+    GhrFixType.commitRecover,
+    Mux(
+      ghrUpdateSignalBundle.exeFixBundle.isExeFixValid,
+      Mux(
+        ghrUpdateSignalBundle.exeFixBundle.exeFixFirstBrTaken,
+        GhrFixType.exeUpdateJump,
+        Mux(ghrUpdateSignalBundle.exeFixBundle.exeFixJumpError, GhrFixType.exeFixJumpError, GhrFixType.exeRecover)
+      ),
+      Mux(ghrUpdateSignalBundle.isPredecoderBranchTaken, GhrFixType.decodeUpdateJump, GhrFixType.decodeBrExcp)
+    )
+  )
+
   // connect fetch target buffer module
   // assign ftbHit = 0
   val ftbModule = Module(new FTB)
@@ -220,12 +243,16 @@ class BPU(
 
   // connect tage Predictor module
   val tagePredictorModule = Module(new TagePredictor)
-  tagePredictorModule.io.pc             := io.pc
-  tageQueryMeta                         := tagePredictorModule.io.tageQueryMeta
-  predictTaken                          := tagePredictorModule.io.predictBranchTaken
-  predictValid                          := tagePredictorModule.io.predictValid
-  tagePredictorModule.io.updatePc       := io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.startPc
-  tagePredictorModule.io.updateInfoPort := tageUpdateInfo
+  tagePredictorModule.io.pc                             := io.pc
+  tageQueryMeta                                         := tagePredictorModule.io.tageQueryMeta
+  predictTaken                                          := tagePredictorModule.io.predictBranchTaken
+  predictValid                                          := tagePredictorModule.io.predictValid
+  tagePredictorModule.io.updatePc                       := io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.startPc
+  tagePredictorModule.io.updateInfoPort                 := tageUpdateInfo
+  tagePredictorModule.io.ghrUpdateNdBundle.bpuSpecTaken := io.bpuFtqPort.ftqP1.predictTaken // bpu predict info
+  tagePredictorModule.io.ghrUpdateNdBundle.bpuSpecValid := mainRedirectValid
+  tagePredictorModule.io.ghrUpdateNdBundle.fixBundle    := ghrFixBundle
+  tagePredictorModule.io.ghrUpdateNdBundle.tageGhrInfo  := io.bpuFtqPort.ftqBpuTrainMeta.tageGhrInfo
 //  tagePredictorModule.io.perfTagHitCounters <> DontCare
 
 }