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Merged
NotTheEndOfTheWorld merged 1 commit into from
Aug 14, 2023
Merged

feat:reduce RAS delay and cost #320

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26 changes: 16 additions & 10 deletions src/src/frontend/FetchTargetQueue.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -242,13 +242,16 @@ class FetchTargetQueue(
io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.fallThroughAddr := ftqBranchMetaRegs(commitFtqId).fallThroughAddr

// commit to ras
io.ftqRasPort.valid := io.commitFtqTrainPort.isTrainValid
io.ftqRasPort.bits.isPush := io.commitFtqTrainPort.branchTakenMeta.branchType === BranchType.call
io.ftqRasPort.bits.isPop := io.commitFtqTrainPort.branchTakenMeta.branchType === BranchType.ret
io.ftqRasPort.bits.callAddr := ftqBranchMetaRegs(commitFtqId).fallThroughAddr
io.ftqRasPort.bits.predictError := ftqBranchMetaRegs(
commitFtqId
).ftbDirty || (io.commitFtqTrainPort.branchTakenMeta.predictedTaken ^ io.commitFtqTrainPort.branchTakenMeta.isTaken)
io.ftqRasPort.valid := RegNext(io.commitFtqTrainPort.isTrainValid, false.B)
io.ftqRasPort.bits.isPush := RegNext(io.commitFtqTrainPort.branchTakenMeta.branchType === BranchType.call, false.B)
io.ftqRasPort.bits.isPop := RegNext(io.commitFtqTrainPort.branchTakenMeta.branchType === BranchType.ret, false.B)
io.ftqRasPort.bits.callAddr := RegNext(ftqBranchMetaRegs(commitFtqId).fallThroughAddr, 0.U)
io.ftqRasPort.bits.predictError := RegNext(
ftqBranchMetaRegs(
commitFtqId
).ftbDirty || (io.commitFtqTrainPort.branchTakenMeta.predictedTaken ^ io.commitFtqTrainPort.branchTakenMeta.isTaken),
false.B
)
// }

// Bpu meta ram
Expand Down Expand Up @@ -314,9 +317,12 @@ class FetchTargetQueue(
io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.jumpTargetAddr := io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateJumpTarget
io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.fallThroughAddr := io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFallThrough

io.ftqRasPort.bits.callAddr := io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFallThrough
io.ftqRasPort.bits.predictError := io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFtbDirty ||
(io.commitFtqTrainPort.branchTakenMeta.predictedTaken ^ io.commitFtqTrainPort.branchTakenMeta.isTaken)
io.ftqRasPort.bits.callAddr := RegNext(io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFallThrough, 0.U)
io.ftqRasPort.bits.predictError := RegNext(
io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFtbDirty ||
(io.commitFtqTrainPort.branchTakenMeta.predictedTaken ^ io.commitFtqTrainPort.branchTakenMeta.isTaken),
false.B
)
}

}
4 changes: 3 additions & 1 deletion src/src/frontend/bpu/RAS.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -67,8 +67,10 @@ class RAS(
}
// Output
if (Param.isOverideRas) {
io.topAddr := Mux(io.predictError, lutram(readIndex), predictLutram(predictReadIndex))
// io.topAddr := Mux(io.predictError, lutram(readIndex), predictLutram(predictReadIndex))
io.topAddr := predictLutram(predictReadIndex)
} else {
io.topAddr := lutram(predictReadIndex)
}

}