Release v1.0.0

What's Changed

• feat: add firtool binary for Windows by @Jim-shop in #1
• fix: upgrade chisel version by @rewired-gh in #2
• fix: upgrade other dependencies by @rewired-gh in #3
• Multiple commits by @rewired-gh in #4
• 早期总体设计 by @rewired-gh in #5
• Remove user-specific configs by @rewired-gh in #10
• AXI总线 by @Jim-shop in #8
• Simple Fetch Stage (1) by @rewired-gh in #11
• fix: fully initialize ports in AXI master by @Jim-shop in #13
• Simple top module connections by @rewired-gh in #12
• Dev yhy by @Chrisqcwx in #15
• the rest part of AXI by @Jim-shop in #14
• fix: misc including things related to scoreboard (WIP) by @rewired-gh in #16
• Add AXI crossbar to Simple Fetch Stage by @Jim-shop in #18
• feat: add insts; refactor: exeStage with state machine by @Chrisqcwx in #19
• feat: refactor alu with state machine and avoid recalculating mul/div when stalling by @Chrisqcwx in #20
• fix: chiplab debug port by @rewired-gh in #22
• refactor: rename MemLoadStoreNdPort -> MemLoadStoreInfoNdPort by @Chrisqcwx in #21
• Integrate with Chiplab (in progress) by @Jim-shop in #24
• refactor: refactor Mul module with booth algorithm and wallance tree. by @Chrisqcwx in #25
• Make difftest possible by @rewired-gh in #26
• feat!: add csr and exceptions. MANY ports modified by @Chrisqcwx in #27
• refactor: rename WbDebugPort --> InstInfoPort by @Chrisqcwx in #28
• Upgrade CIRCT related stuff by @rewired-gh in #29
• feat: add many many many CsrRegs ; delect divisorZeroException by @Chrisqcwx in #30
• refactor: move some bundles' location; feat: add csr decode and assign; fix: fix state behavior error in exeStage by @Chrisqcwx in #31
• feat: add scoreboard for csr by @Chrisqcwx in #32
• Baby Step 1: DCache (WIP) by @rewired-gh in #33
• Baby Step 2: DCache (WIP) by @rewired-gh in #34
• Baby Step 3: DCache (WIP) by @rewired-gh in #36
• Project cleanup by @rewired-gh in #37
• fix: bugs from previous refactor by @rewired-gh in #38
• feat: add data forward by @Chrisqcwx in #39
• refactor!!: decode in IssueStage -> decode in InstQueue; jump branch new Pc calc by exe send to Ctrl Unit to decide which new pc by @Chrisqcwx in #41
• Mem stage port by @rewired-gh in #44
• Remove clutters by @rewired-gh in #45
• Mem Stage by @rewired-gh in #46
• Difftest Compatibility (Basic) by @Jim-shop in #40
• (CAN MERGE)remove data forward temporily; feat: add BiInstQueue, BiIssueStage, RobStage; add memAccessPort in ExeStage by @Chrisqcwx in #43
• Memory stage related stuffs (Episode 1) by @rewired-gh in #47
• refactor: adapt to the new MemRequestNdPort (add a port: isUnsigned); fix: fix some bugs in rob by @Chrisqcwx in #48
• refactor: refactor some bundle port with parameters; kill the writeEn when writeAddr is x0 by @Chrisqcwx in #49
• fix: fix Difftest valid signal connection by @Jim-shop in #52
• fix: difftest connections by @rewired-gh in #55
• fix: Bug flush(#51) by @Jim-shop in #54
• (Drafted) Chiplab automation by @rewired-gh in #53
• fix: fix bug in inst sra and bl by @Chrisqcwx in #56
• fix: fix bug in Cu by @Chrisqcwx in #57
• TLB implementation by @rewired-gh in #50
• feat: a little tool for 'rebasing' branch by @rewired-gh in #60
• feat: make 'rebasing' safer by @rewired-gh in #61
• feat: 以黑盒形式接入AXI Crossbar by @Jim-shop in #64
• fix: unmangle most stuffs by @rewired-gh in #66
• Fix comb loop by @rewired-gh in #67
• Remove crossbar connection and fix decode instruction matched by @rewired-gh in #70
• 修Crossbar by @Jim-shop in #71
• 再修 Crossbar by @Jim-shop in #72
• Fix several critical things by @rewired-gh in #73
• Fix PC jump in SimpleFetchStage by @rewired-gh in #76
• fix: something by @rewired-gh in #77
• feat: BaseStage infrastructure by @rewired-gh in #79
• fix: several bugs by @rewired-gh in #80
• Fix ready valid by @Jim-shop in #83
• Dev frontend add ICache and test by @NotTheEndOfTheWorld in #82
• feat: add syscall and brk in ExeStage by @Chrisqcwx in #88
• fix: inst sltui decode err by @Chrisqcwx in #89
• fix: mul & div error; test lab6 success by @Chrisqcwx in #94
• feat: add excp & ertn difftest ; fix typo ; refactor some comments by @Chrisqcwx in #95
• Connect difftest by @rewired-gh in #96
• fix: csr -> instinfo in BiInstQueue by @Chrisqcwx in #99
• Revert "fix: csr -> instinfo in BiInstQueue" by @rewired-gh in #101
• Introduce ICache and fix cache related bugs by @NotTheEndOfTheWorld in #100
• Address translation related by @rewired-gh in #104
• Eliminate memory write structure hazard by @rewired-gh in #106
• fix issue bug & refactor Scoreboard by @Chrisqcwx in #103
• feat: tune params by @rewired-gh in #110
• Fix firtool for debug by @rewired-gh in #111
• Refactor BiIssueStage with MultiBaseStage by @Chrisqcwx in #109
• Fix "divisor greater than dividend" by @rewired-gh in #113
• Fix CSR maintenance instruction implementation by @rewired-gh in #114
• Literally fix csr instruction by @rewired-gh in #116
• Connect difftest csr_rstat by @rewired-gh in #117
• fix ertn bug by @Chrisqcwx in #118
• decode for tlb; refactor csr scoreboard by @Chrisqcwx in #120
• Connect difftest, implement cache maintenance, and refactor DCache to use BRAM by @rewired-gh in #122
• Migrate to use BRAM by @rewired-gh in #129
• Add BRAM blackbox by @rewired-gh in #130
• connect difftest; add interrupt; adef exception in exe (temp, but need to be implement in frontend) by @Chrisqcwx in #123
• Fix a tiny bug in DCache by @rewired-gh in #131
• refactor: etrn jump from wb -> ExeStage by @Chrisqcwx in #132
• fix rdcnt error by @Chrisqcwx in #133
• Fix DCache read-write selection in some corner cases by @rewired-gh in #134
• feat: load/store can only issue on one pipeline by @Chrisqcwx in #136
• refactor: BiInstQueue -> MultiInstQueue by @Chrisqcwx in #138
• refactor: abstract the multi-queue out by @Chrisqcwx in #140
• feat: add idle inst by @Chrisqcwx in #141
• add excption for frontend by @Chrisqcwx in #142
• refactor excp for frontend by @Chrisqcwx in #143
• refactor flush by @Chrisqcwx in #144
• Refactor InstFetch; Add InstAddrTransStage by @NotTheEndOfTheWorld in #139
• multi issue by @Chrisqcwx in #147
• refactor: kill all Cats in Csr by @Chrisqcwx in #148
• Refactor csr by @Chrisqcwx in #149
• fix: badv assignment; refactor: isExceptionValid -> exceptionPos; writeback -> commit by @Chrisqcwx in #151
• 2-commit by @Chrisqcwx in #153
• refactor: optimize InstQueue, IssueStage, ExeStage by @Chrisqcwx in #159
• feat: change CI by @rewired-gh in #157
• Clean up codebase by @rewired-gh in #161
• refactor: instQueue enqueue with 1 ready-valid by @Chrisqcwx in #164
• Implement TLB maintenance by @rewired-gh in #162
• fix: flush and jump for fetch related CSR changes by @rewired-gh in #167
• fix frontend pass exception info bug by @NotTheEndOfTheWorld in #171
• add a queue between decode and dispatch & fix some parameter error in distributedQueue by @Chrisqcwx in #160
• Tlb excp by @Chrisqcwx in #172
• Frontend instruction blocking by @rewired-gh in #173
• Integrate CACOP by @rewired-gh in #174
• fix: vaddr assignment in ExeForMemStage by @Chrisqcwx in #175
• add idle by @Chrisqcwx in #176
• fix: atomic store by @rewired-gh in #177
• refactor with parallel commit & no depend on difftest info by @Chrisqcwx in #178
• Fix flush and jump by @rewired-gh in #179
• [WIP] fix: instruction invalid when pc is 0 by @rewired-gh in #180
• feat: add ipe exception by @Chrisqcwx in #181
• Fix AXI dynamic size when uncached by @rewired-gh in #183
• Fix AXI 3 WID by @rewired-gh in #184
• Fix many things by @rewired-gh in #182
• [WIP] Fix for Linux (Stage 1) by @rewired-gh in #185
• introduce multi fetch inst by @NotTheEndOfTheWorld in #188
• Split IssueStage -> RenameStage + DispatchStage by @Chrisqcwx in #189
• feat: CACOP workaround by @rewired-gh in #190
• fix: small optimization by @rewired-gh in #191
• fix: remove dependence on rlast by @rewired-gh in #192
• Add uncached address workaround by @rewired-gh in #193
• Refactor: replace multiQueue with distributedQueue in Rob by @Chrisqcwx in #194
• Fix CACOP in DCache by @rewired-gh in #195
• Fix a small bug by @rewired-gh in #196
• fix: cache related problems by @rewired-gh in #198
• Fix a CSR bug by @Jim-shop in #197
• Fix commit by @rewired-gh in #199
• Cache write back to back by @rewired-gh in #201
• Fix cache last write assertion by @rewired-gh in #202
• Fix mainly TLB related problems by @rewired-gh in #203
• Fix asid by @Chrisqcwx in #205
• Fix csr by @Chrisqcwx in #206
• Fix csr by @Chrisqcwx in #207
• abstract reservation station out by @Chrisqcwx in #208
• feat: allow load with no hazard when store queue is not empty by @rewired-gh in #210
• feat: add Out-of-Order Issue by @Chrisqcwx in #211
• Improve memory related stages by @rewired-gh in #212
• remove csr write port in InstInfo, store in csr score board by @Chrisqcwx in #213
• simplify rename by @Chrisqcwx in #214
• Some improvement by @rewired-gh in #216
• Refactor div by @Chrisqcwx in #218
• Refactor inst queue with pass through by @Chrisqcwx in #219
• 发射前移 by @Chrisqcwx in #220
• Improve performance by @rewired-gh in #221
• Refactor mul by @Chrisqcwx in #222
• add frontend by @Chrisqcwx in #223
• feat: add option for issue insts with same write reg by @Chrisqcwx in #224
• fix: match table change when no ready by @Chrisqcwx in #226
• feat: parameterize by @rewired-gh in #227
• add out of order issue by @Chrisqcwx in #228
• fix: AXI multiple transactions by @rewired-gh in #229
• refactor ftq,instAddr in Frontend by @Chrisqcwx in #225
• refactor addrTransStage: get rid of saveIn by @Chrisqcwx in #231
• fix: change to correct parameters by @rewired-gh in #232
• refactor OoO by @Chrisqcwx in #233
• fix: flush hazard by @rewired-gh in #235
• fix: dirty of last write action by @rewired-gh in #236
• fix: false cache write-back of cache maintenance by @rewired-gh in #237
• Fix DCache by @rewired-gh in #238
• fix: cache dirty bit pass-through condition by @rewired-gh in #239
• fix: cache maintenance hazard by @rewired-gh in #240
• fix: only use predict branch when is last in block by @Chrisqcwx in #242
• only predict branch when is last in block in frontend by @Chrisqcwx in #243
• fix: mis predict assignment in exe by @Chrisqcwx in #244
• fix csr value when no exist by @Chrisqcwx in #245
• feat: add dbar by @Chrisqcwx in #241
• fix: remove jump assign when tlb by @Chrisqcwx in #246
• fix: 4MB page size translation by @rewired-gh in #247
• fix: not allow CACOP when not hit by @rewired-gh in #248
• fix: no commit to ftq when excp by @Chrisqcwx in #249
• feat: add redirect in decode by @Chrisqcwx in #250
• Fix branch by @Chrisqcwx in #251
• fix error redirect in decode by @Chrisqcwx in #252
• fix: redirect assignment error by @Chrisqcwx in #253
• fix tagePredictor;react ftq,instAddrStage with low line delay by @NotTheEndOfTheWorld in #254
• fix: change csr score board when redirect from decode error by @Chrisqcwx in #255
• fix: CACOP count down flush by @rewired-gh in #256
• feat: add write back pass through wake up detection by @Chrisqcwx in #257
• fix:branch predict update bug by @NotTheEndOfTheWorld in #258
• Reapply out-of-order instruction issue by @rewired-gh in #259
• Add uncached flag by @rewired-gh in #260
• fix: timer enable by @Chrisqcwx in #262
• feat: add uncached address ranges by @rewired-gh in #261
• simplify match table in rob by @Chrisqcwx in #263
• Branch predict by @rewired-gh in #264
• Fix interrupt by @rewired-gh in #265
• fix：tagPredicater only use longest history bug by @NotTheEndOfTheWorld in #266
• refactor refetch & interrupt by @Chrisqcwx in #267
• Fix TLBFILL entry selection strategy by @rewired-gh in #268
• feat:change tagePredictor param by @NotTheEndOfTheWorld in #270
• fix redirect blocking error & refactor: remove unuse logic in Cu by @Chrisqcwx in #271
• feat: add option for optimized by MultiMux by @Chrisqcwx in #272
• refactor: choose new pc in delay by @Chrisqcwx in #273
• Tune cache parameters, reduce cycles when not using TLB, and delay MMIO load by @rewired-gh in #274
• feat:icache send dateLine to instresStage by @NotTheEndOfTheWorld in #275
• fix and refactor TagePredictor by @Chrisqcwx in #276
• Introduce PredecoderStage；add branch counter by @NotTheEndOfTheWorld in #277
• feat: add pmu by @Chrisqcwx in #278
• add option for wake up pass exe & add pmu by @Chrisqcwx in #279
• fix: pmu cond err by @Chrisqcwx in #280
• refactor & fix pmu by @Chrisqcwx in #281
• refactor ooo by @Chrisqcwx in #282
• feat: add option for inst queue connect by @Chrisqcwx in #284
• Exe jump by @Chrisqcwx in #286
• fix: condition of CACOP writing-back done by @rewired-gh in #287
• add option for optimize by LVT of reg data by @Chrisqcwx in #288
• remove lvt by @Chrisqcwx in #289
• refactor match table by @Chrisqcwx in #291
• feat: not ignore AddrTransStage by @rewired-gh in #290
• refactor: remove inst, pc, vaddr in inst info by @Chrisqcwx in #283
• Some improvements by @rewired-gh in #292
• fix some bugs in addrTrans & test by @Chrisqcwx in #293
• feat: shrink cache by @rewired-gh in #294
• fix: exception handling for CACOP and no CACOP for uncached address by @rewired-gh in #295
• fix: ICache uses parameters from DCache by @rewired-gh in #296
• feat: add PMU variables for memory related component and reduce `ExeF… by @rewired-gh in #297
• Introduce predict RAS by @NotTheEndOfTheWorld in #298
• refactor: rename file by @Chrisqcwx in #299
• fix:return predict less then call by @NotTheEndOfTheWorld in #300
• move some file by @Chrisqcwx in #301
• Param FTB update ret when RAS mispredict by @NotTheEndOfTheWorld in #303
• add some new components in backend & refactor CoreCpuTop by @Chrisqcwx in #302
• fix:clear FTB entry when a nonBranch inst predict taken by @NotTheEndOfTheWorld in #304
• feat: add simple pipeline by @Chrisqcwx in #305
• fix: Cu port conflict between simple & complex by @Chrisqcwx in #306
• fix:FTB do not train immJump because predecode predirect corect by @NotTheEndOfTheWorld in #307
• refactor: data forward by @Chrisqcwx in #308
• fix: idle block by @Chrisqcwx in #309
• refactor: split decode and issue by @Chrisqcwx in #310
• refactor backend train bpu by @NotTheEndOfTheWorld in #311
• Introduce speculative update global history by @NotTheEndOfTheWorld in #313
• refactor exe op by @Chrisqcwx in #314
• feat: add option for main exe write back early by @Chrisqcwx in #315
• add OoO by @Chrisqcwx in #316
• feat: add option for dispatch to 3 unit by @Chrisqcwx in #317
• refactor alu by @Chrisqcwx in #318
• CutInstAddrStage，reactor branch train by @NotTheEndOfTheWorld in #319
• feat:reduce RAS delay and cost by @NotTheEndOfTheWorld in #320
• Reduce Ftb cost by @NotTheEndOfTheWorld in #321
• refactor issue queue by @Chrisqcwx in #322
• Reduce train cost by @Chrisqcwx in #323
• Fix dbar by @Chrisqcwx in #324
• fix: jump when flush by @Chrisqcwx in #325
• fix: output no valid when flush in main exe by @Chrisqcwx in #326
• fix:preDecoder should not change errorJump fetchLength by @NotTheEndOfTheWorld in #327

Full Changelog: https://github.com/Invalid-Syntax-NSCSCC/invalid-cpu/commits/v1.0.0