Feature: Add ImageInvert block and Fix Synthesis Port Mapping

[Khushi281300]

This PR addresses the expansion of the OpenCV block library by adding the ImageInvert block and resolving a critical bug in the code synthesis engine.

Key Changes

1. New ImageInvert Block:

   • Added ImageInvert.json schema to the opencv collection with input ports for Img and Enable.
   • Implemented color inversion using cv2.bitwise_not() in the module logic.

2. Synthesis Engine Bug Fix (synthesis.py):

   • Problem: The engine previously only supported UUIDs for port identification, causing wires with named labels (like "Img") to fail during collapsing/synthesis.
   • Solution: Patched synthesis.py to allow port lookups by both UUID and Name, ensuring seamless data flow for all blocks.

3. Improved Code Generation (main.py template):

   • Added unique session IDs to shared memory wire names to prevent "broadcast shape" errors caused by stale memory buffers on Windows.

4. Registry Update:

   • Registered the new block in the collection-factory.tsx.

Verification

• Created a local pipeline: Camera -> ImageInvert -> Screen
• Successfully verified that the live camera feed was inverted without errors.

Recording 2026-03-23 230106.zip

[toshan-luktuke]

Hey Khushi, 700+ lines is not really a reviewable PR size. If you want to contribute just the ImageInvert Block then please open a separate PR to do so, and we can take a look.

UUID based wire mapping is a feature, we don't want to map on block names since they can be repeated

[Khushi281300]

Hey Khushi, 700+ lines is not really a reviewable PR size. If you want to contribute just the ImageInvert Block then please open a separate PR to do so, and we can take a look.

UUID based wire mapping is a feature, we don't want to map on block names since they can be repeated

Hey @toshan-luktuke,

Thank you for the review and the context!
I'll close this PR and open a new, clean one that only includes the new ImageInvert block (JSON schema, Python logic, and UI registry update), without any modifications to the core synthesis engine (synthesis.py) or the main template (main.py). I'll also ensure my block properly uses the UUID mapping as intended instead of relying on names.
Thanks again for the guidance!