- BGR block (sizing, calculations, etc.) - (current bgr sizing to be included in the report)
- Change BGR architecture (cascoded,etc. ) - to increase PSRR magnitude
- Fix PSRR across PVT
- Capture the behavior of LDO parameters across PVT corners (ex: overshoots, PSRR, PM, UGB, gain, load regulation, load transient, etc.)
- Update report with explanations for all theoretical calculations and individual block simulation results, compensation technique, sizings, etc.
- Add circuit diagrams to the report
- Do Trimming for 5 corners (cross corners not required)
- Design LDO without using Miller compensation, use other compensations
- Design for gain bandwidth = 2MHz and PM > 45 degrees
- Meet all the design specifications
- Include enable switches for LDO
- Create a symbol for the LDO
- Add a decoupling capacitor at the output node of BGR to prevent spikes in the output due to any spikes in vdd
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