This repository contains the design, simulation, and analysis of a precision sub-regulator circuit. This project was conducted as part of the CMOS References and Regulators (EC2.410) curriculum, utilizing the architecture concepts covered in the lecture on October 23rd.
The primary objective is to design a robust regulator capable of handling specific load transients and process variations while maintaining high stability and Power Supply Rejection Ratio (PSRR).
The sub-regulator is designed to meet the following electrical constraints:
| Parameter | Specification | Conditions |
|---|---|---|
| Input Voltage | 3.3V | Range: ±10% (2.97V - 3.63V) |
| Output Voltage | 2.8V | Target |
| Load Current | 0 to 1mA | Nominal Range |
| Quiescent Current | < 500 µA | No Load condition |
| PVT Variation | < 5 mV | Across Process, Voltage, Temperature |
| Monte Carlo (MC) | < ±1.5% | Random Variation |
| Phase Margin | > 45° | Full Load |
| UGB | > 1 MHz | Full Load |
| PSRR (DC) | > 40 dB | |
| PSRR (High Freq) | > 0 dB | Must not drop below 0dB at any frequency |
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Impulse Response: Capable of handling a sudden 6mA impulse on top of a 1mA static load with a maximum undershoot of 25mV.
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De-coupling Capacitor: optimized to meet the undershoot specification.
The final report and simulation logs located in this repository cover the following characterizations:
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PVT Analysis: Static variation in output voltage across corners. (4-bit Resistive Trimming has to be performed for 5 corners)
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Monte Carlo Analysis: Random variation histogram and statistical summary (Mean/Sigma) relative to the ±1.5% target.
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Load Transients: - 0 to 1mA step response.
- Impulse Response: 6mA impulse (superimposed on 1mA load) to verify <25mV undershoot.
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Settling Time: Analysis of output recovery time at no-load conditions.
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Load Profile: Plot of Output Voltage vs. Time alongside the applied Load Current profile.
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Loop Gain & Phase: Bode plots showing Phase Margin (>45°) and UGB (>1MHz).
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Bandwidth: 3dB Bandwidth extraction across PVT corners.
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DC Load Regulation: Output Voltage vs. Load Current plot across PVT.
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PSRR: Magnitude plot vs. Frequency (verifying >40dB at DC and >0dB globally).
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Design: Cadence Virtuoso, TSMC 180nm PDK
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Simulator: Spectre
- Analog Integrated Circuit Design, 2nd Edition (Tony Chan Carusone, David A. Johns,Kenneth W. Martin) - Chapter 7
- CMOS Analog Circuit Design, 3rd Edition ( Phillip E. Allen, Douglas R. Holberg) - Section 5.2.7
- Design of Analog CMOS Integrated Circuits, 2nd Edition (Behzad Razavi) - Chapter 5,10,12
- Madhan Sai Krishna