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[https://nvbugs/6093911][fix] Fix disagg gen-only benchmark hang under ADP router imbalance - #13347

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chienchunhung:fix/disagg-fill-gate-rewrite
May 20, 2026
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[https://nvbugs/6093911][fix] Fix disagg gen-only benchmark hang under ADP router imbalance#13347
chienchunhung merged 6 commits into
NVIDIA:mainfrom
chienchunhung:fix/disagg-fill-gate-rewrite

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@chienchunhung chienchunhung commented Apr 22, 2026

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Summary by CodeRabbit

  • Bug Fixes

    • Improved benchmark disaggregation fill gate to determine readiness based on executor state rather than request counts, ensuring more accurate synchronization across distributed ranks.
    • Enhanced diagnostic logging to report transfer status and request state information.
  • Tests

    • Updated and expanded test coverage for state-based readiness validation, including new regression tests for distributed training scenarios.

Summary

Fixes four ADP/NIXL regressions PR #12208 introduced when it removed the blocking fill loop, and corrects a long-latent KV oversubscription in the Kimi-2 8k1k perf-sanity test config that #12208's fill-phase changes exposed.

Production fixes (2 commits)

PR #12208 replaced the blocking fill loop with a non-blocking gate to fix an MPI hard deadlock. The replacement was correct for MPI but introduced four ADP/NIXL-side regressions, all addressed here:

  • State-based fill gate — count-based predicate is unsatisfiable under ADP per-rank rebalancing. Replaced with (num_fetched ≥ queue_size) ∧ (no active req in INIT/TRANS) ∧ (no transceiver pending). Fires uniformly across ranks.
  • ADP router hard cap at max_num_active_requests (= per-rank max_batch_size) on both DefaultADPRouter and KVCacheAwareADPRouter — composes with upstream's fair_share_multiplier loose cap. Fixes nvbug 6071070; without it, bulk admission can route past max_batch_size and leave excess requests stuck in INIT.
  • Fail-fast suppression during fill — PR [None][fix] return an explicit error if the requests can't be schedul… #12206's fail-fast was tripping on transient bulk-fetch state (some requests in INIT while others transfer). Resumes after the gate opens.
  • tp_size-per-iter admission throttle in _pop_from_waiting_queue — restores the pre-[TRTLLM-11492][fix] Fix benchmark disagg deadlock by eliminating blocking fill loop #12208 conservative admission rate without reintroducing the blocking pattern. Scoped to non-warmup benchmark fill.

Test config fix (1 commit): Kimi-2 GEN KV fraction 0.6 → 0.78

Memory math (B200/GB200, 184 GiB HBM)

0.6 (upstream) 0.78 (this PR)
KV pool 61.4 GiB 79.8 GiB
KV tokens / rank 1,875,008 2,437,504
Required at bs=256 × max_seq_len=9256 2,369,536 (same)
Sequences fit / 256 203 263
Headroom for transients ~40 GiB ~22 GiB

At 0.6, only 203 of 256 max-batch sequences fit per rank — 53 are perpetually paused, costing ~21 % of decode throughput across the entire run. 0.78 is the floor that fits the workload while preserving the ~22 GiB needed for NIXL receive buffers, NCCL workspace, EPLB layer churn, and CUDA caching-allocator fragmentation.

Why the test was passing before PR #12208

Same YAML, same oversubscription — but timing differed:

The test was always running on luck. Bumping to 0.78 makes it do what it claims (bs=256 steady-state) instead of depending on the right side of a 2–5 min margin.

Why this YAML change is bundled into this PR

The bump is a one-line test-config correctness fix that stands on its own — it would have been correct at any point in the test's lifetime. It belongs here because (a) the gate fixes are necessary but not sufficient for the Kimi-2 CI to reach green, and (b) the two changes share the same failure narrative.

Test coverage

Production fixes are covered by tests/unittest/_torch/executor/test_benchmark_disagg.py (10 test classes, 28 tests, no GPU required):

Production fix Coverage
State-based fill gate TestFillCompleteStateBased (4 tests, parameterized over the predicate's truth table), TestFillCompleteADP (3 tests, cross-rank allgather), TestFillCompleteADPRouterImbalance (2 tests, per-rank rebalancing edge cases), TestCheckBenchmarkDisaggGate (3 tests, wait-loop behavior), TestCanForwardGating (parameterized initial state)
ADP router hard cap TestADPRouterPerRankCap (3 tests, parameterized over both DefaultADPRouter and KVCacheAwareADPRouter: cap applied at max, no rank exceeds, no-op below max)
Fail-fast suppression during fill TestFailFastSuppressedDuringFill (3 tests: suppressed during fill, resumes after, full (fill_active × is_warmup) matrix)
tp_size-per-iter admission throttle TestBenchmarkFillAdmissionFlowControl (2 tests, parameterized over tp_size ∈ {1, 4, 32}: cap applied during fill, full capacity used after)
Adjacent invariants TestPadAttentionDpDummyBenchmarkDisagg (4 tests, dummy-request skip during fill), TestPrepareAndScheduleBatchNoBlock (1 test, fetch called once per iter)
End-to-end lifecycle TestFillPhaseEndToEnd::test_full_lifecycle (admission-cap → KV-transfer-complete → gate-opens → normal admission, exercising both production code paths together)

The Kimi-2 perf-sanity test has been verified separately: https://nvbugspro.nvidia.com/bug/6093911?commentNumber=9

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  • Any new dependencies have been scanned for license and vulnerabilities

  • CODEOWNERS updated if ownership changes

  • Documentation updated as needed

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chienchunhung force-pushed the fix/disagg-fill-gate-rewrite branch from 16533e3 to f98e2fd Compare April 23, 2026 18:20
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chienchunhung marked this pull request as ready for review April 24, 2026 03:10
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📝 Walkthrough

Walkthrough

Refactors the benchmark-disagg fill gate readiness logic from counting generation requests to evaluating executor state, including active request states and KV cache transfer completion. In ADP mode, synchronizes readiness across TP ranks using allgather. Updates corresponding test suite to validate state-based predicate behavior and adds regression coverage for rank skew scenarios.

Changes

Cohort / File(s) Summary
Core Predicate Logic
tensorrt_llm/_torch/pyexecutor/py_executor.py
Refactored _is_benchmark_disagg_fill_complete from count-based thresholds to state-based evaluation. Now checks: (1) sufficient fetched requests, (2) active requests past INIT/TRANS_IN_PROGRESS states, (3) KV cache transceiver completion status. In ADP mode, synchronizes conditions (B) and (C) across TP ranks via tp_allgather. Updated logging to report rank-local state counts and transfer status.
Test Suite Updates
tests/unittest/_torch/executor/test_benchmark_disagg.py
Comprehensively refactored tests to validate state-based predicate instead of count-based logic. Removed tests depending on old batch construction semantics. Updated ADP test coverage to verify tp_allgather behavior. Simplified dummy padding tests. Added regression suite for nvbug 6071070 validating predicate blocking under ADP router skew and INIT overflow scenarios.

Estimated code review effort

🎯 4 (Complex) | ⏱️ ~45 minutes

Possibly related PRs

Suggested reviewers

  • pcastonguay
🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 21.74% which is insufficient. The required threshold is 80.00%. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (4 passed)
Check name Status Explanation
Title check ✅ Passed The title correctly identifies the bug fix (disagg gen-only benchmark hang) and the root cause context (ADP router imbalance), directly matching the PR's primary objective.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
Description check ✅ Passed PR description comprehensively explains the problem, solution, test coverage, and production fixes with detailed context on regressions and memory math.

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🧹 Nitpick comments (1)
tests/unittest/_torch/executor/test_benchmark_disagg.py (1)

233-233: Optional: Linter warning about multiplication sign character.

Static analysis flags the × character as ambiguous (RUF002). While the mathematical notation is clearer for readers, you can silence this by using ASCII x or escaping if strict linting is required.

-    (e.g. 31×256 + 1×255 = 8191 < 8192). The new state-based predicate
+    (e.g. 31*256 + 1*255 = 8191 < 8192). The new state-based predicate
🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@tests/unittest/_torch/executor/test_benchmark_disagg.py` at line 233, Replace
the non-ASCII multiplication character in the test string (e.g. "31×256 + 1×255
= 8191 < 8192") with an ASCII 'x' or escape it to satisfy the linter; update the
literal in tests/unittest/_torch/executor/test_benchmark_disagg.py so
occurrences of '×' become 'x' (or an escaped sequence) to silence RUF002 while
preserving the intended text.
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.

Nitpick comments:
In `@tests/unittest/_torch/executor/test_benchmark_disagg.py`:
- Line 233: Replace the non-ASCII multiplication character in the test string
(e.g. "31×256 + 1×255 = 8191 < 8192") with an ASCII 'x' or escape it to satisfy
the linter; update the literal in
tests/unittest/_torch/executor/test_benchmark_disagg.py so occurrences of '×'
become 'x' (or an escaped sequence) to silence RUF002 while preserving the
intended text.

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📥 Commits

Reviewing files that changed from the base of the PR and between a492e5b and f98e2fd.

📒 Files selected for processing (2)
  • tensorrt_llm/_torch/pyexecutor/py_executor.py
  • tests/unittest/_torch/executor/test_benchmark_disagg.py

chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request Apr 27, 2026
Update the benchmark disagg fill design docs to reflect the final
three-part PR NVIDIA#13347 fix: state-based gate, ADP router cap, and
fill-phase fail-fast suppression. Add a dedicated note explaining why
PR NVIDIA#12206 fail-fast must be disabled while the benchmark fill barrier is
active.

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
Made-with: Cursor
chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request Apr 28, 2026
…stuck-state finding

Document the v2.2 follow-up to PR NVIDIA#13347 and a separate latent issue
discovered while validating it locally:

* 07-fill-phase-flow-control.md (new): v2.2 production fix. Reintroduces
  the per-iteration `tp_size` admission cap that PR NVIDIA#12091 had as part
  of the blocking fill loop, and that PR NVIDIA#12208 implicitly removed when
  it eliminated that loop. Without it, on `dep32 × bs256 == con8192`
  the GEN server is OOM-killed during burst admission before any KV
  transfer can drain. Includes safety analysis, test coverage notes,
  and a tunable-cap discussion.

* 08-fill-phase-stuck-state-finding.md (new): a separate latent
  deadlock observed during local 8-GPU validation, where the
  state-based gate stays closed because some active requests remain in
  INIT after CTX has finished prefilling. Explicitly framed as
  independent of v2.1 / v2.2 (with a per-patch coverage table proving
  none of those patches touch the deadlock's mechanism), with repro
  instructions and recommended next steps.

* README.md: lineage table gains a v2.2 row; current-state section now
  enumerates four issues with v2.1/v2.2 attribution; documents table
  and reading order updated; "Relationship between the steps" notes
  v2.1 and v2.2 both fall under Step 1.

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
Made-with: Cursor
chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request Apr 28, 2026
…VIDIA#13347

Update the design docs to reflect that the v2.2 fill-phase admission cap
ships in PR NVIDIA#13347 alongside the v2.1 three-part fix, instead of as a
separate follow-up PR. The PR's CI gate cannot pass without v2.2
anyway, so the four commits all land together as fixes for the same
nvbug-tracked wide-EP Kimi failure.

Changes:
* README.md: current-state section, lineage table v2.2 row, reading
  order, and "Relationship between the steps" all now reference
  PR NVIDIA#13347 as the home for both v2.1 and v2.2.
* 07-fill-phase-flow-control.md: header PR reference updated from
  "follow-up #TBD" to "PR NVIDIA#13347 (4th commit)".
* 08-fill-phase-stuck-state-finding.md: status line clarified to
  reference both v2.1 and v2.2 as the patches this finding is
  independent of.

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
Made-with: Cursor
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chienchunhung force-pushed the fix/disagg-fill-gate-rewrite branch from 75d5c33 to 2cce23b Compare April 28, 2026 05:57
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chienchunhung marked this pull request as draft April 28, 2026 06:04
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chienchunhung force-pushed the fix/disagg-fill-gate-rewrite branch from 56bd785 to a2c6107 Compare April 29, 2026 17:12
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Some tests seem to fail due to your changes. For example:


[2026-04-30T01:31:33.474Z] FAILED unittest/DGX_B200-PyTorch-2/unittest/_torch/executor/test_benchmark_disagg.py::TestADPRouterPerRankCap::test_cap_not_applied_when_below_max[KVCacheAwareADPRouter] - assert 4 == 2

Also the release-check job is failing. Could you take a look?

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chienchunhung force-pushed the fix/disagg-fill-gate-rewrite branch 2 times, most recently from f2bd50b to d408754 Compare May 1, 2026 01:47
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Some tests seem to fail due to your changes. For example:


[2026-04-30T01:31:33.474Z] FAILED unittest/DGX_B200-PyTorch-2/unittest/_torch/executor/test_benchmark_disagg.py::TestADPRouterPerRankCap::test_cap_not_applied_when_below_max[KVCacheAwareADPRouter] - assert 4 == 2

Some of the new tests introduced by this PR failed after rebasing to the latest HEAD; updated the tests.

Also the release-check job is failing. Could you take a look?

Yup over the past few days I have been working closely with QA on the Kimi2 test.

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chienchunhung merged commit ef160ad into NVIDIA:main May 20, 2026
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xxi-nv pushed a commit to xxi-nv/TensorRT-LLM that referenced this pull request May 22, 2026
…r ADP router imbalance (NVIDIA#13347)

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
bmarimuthu-nv pushed a commit to nv-auto-deploy/TensorRT-LLM that referenced this pull request May 28, 2026
…r ADP router imbalance (NVIDIA#13347)

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
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