[TRTLLM-12183][chore] Move bf16/auto precision variants from pre-merge to post-merge

[QiJune]

Motivation

For test groups covering the same model / config across multiple precisions, the low-precision variants (fp8, nvfp4, w4, etc.) carry most of the pre-merge signal — accuracy and perf regressions tend to surface there first. The higher-precision variants (bfloat16, auto) are more stable and mainly serve as a secondary safety net, which fits post-merge coverage well.

This PR applies that principle across four test-db files: keep the low-precision variants in pre-merge; move the corresponding bf16/auto variants to post-merge.

Pre-merge impact

Measured on the last 7 days of L0_MergeRequest[_PR] runs (PASSED only): ~3,100 GPU-seconds (~52 min) of test work removed per pre-merge run.

• GB200-4_GPUs-PyTorch-1: ~861 s saved
• GB200-4_GPUs-PyTorch-2: ~705 s saved
• DGX_B200-PyTorch-1/2/3 (sharded): ~613 s total
• DGX_H100-4_GPUs-PyTorch-GptOss-1: ~375 s saved
• DGX_H100-PyTorch-1/2/3/4 (sharded): ~234 s total
• H100_PCIe-PyTorch-Ray-1: ~144 s saved
• DGX_H100-4_GPUs-PyTorch-Others-1/2: ~170 s saved

Risk Evaluation

Pass rates on pre-merge over the last 7 days — and the failures when present turn out to be infra noise, not real product regressions:

1
Test: test_bfloat16[TRTLLM-compile=True]
Total: 296
Pass: 296
Fail: 0
Skip: 0
Pass rate (exec'd): 100%
Notes: —
────────────────────────────────────────
2
Test: test_bfloat16_4gpus[tp4-FLASHINFER-compile=False]
Total: 125
Pass: 125
Fail: 0
Skip: 0
Pass rate (exec'd): 100%
Notes: —
────────────────────────────────────────
3
Test: test_bfloat16_4gpus[tp4-TRTLLM-compile=True]
Total: 99
Pass: 99
Fail: 0
Skip: 0
Pass rate (exec'd): 100%
Notes: —
────────────────────────────────────────
4
Test: test_w4a16[dp4-auto]
Total: 234
Pass: 131
Fail: 0
Skip: 103
Pass rate (exec'd): 100%
Notes: 103 skipped (conditional)
────────────────────────────────────────
5
Test: test_w4_1gpu[v1_kv_cache-trtllm-auto]
Total: 298
Pass: 296
Fail: 2
Skip: 0
Pass rate (exec'd): 99.3%
Notes: —
────────────────────────────────────────
6
Test: test_w4_1gpu[v2_kv_cache-trtllm-auto]
Total: 297
Pass: 295
Fail: 2
Skip: 0
Pass rate (exec'd): 99.3%
Notes: —
────────────────────────────────────────
7
Test: test_bfloat16_4gpus[tp2pp2-TRTLLM-compile=True]
Total: 128
Pass: 127
Fail: 1
Skip: 0
Pass rate (exec'd): 99.2%
Notes: —
────────────────────────────────────────
8
Test: test_bfloat16_4gpus[tp2pp2-TRTLLM-compile=False]
Total: 126
Pass: 125
Fail: 1
Skip: 0
Pass rate (exec'd): 99.2%
Notes: —
────────────────────────────────────────
9
Test: TestQwen3_5_35B_A3B::test_bf16
Total: 292
Pass: 289
Fail: 3
Skip: 0
Pass rate (exec'd): 99.0%
Notes: —
────────────────────────────────────────
10
Test: test_bfloat16[TRTLLM-compile=False]
Total: 643
Pass: 618
Fail: 25
Skip: 0
Pass rate (exec'd): 96.1%
Notes: All 25 failures = Ray ImportError: PlacementGroupSch... —
Ray-library infra issue, not product signal
────────────────────────────────────────
11
Test: test_w4_4gpus[v1_kv_cache-dp4-trtllm-auto]
Total: 113
Pass: 106
Fail: 7
Skip: 0
Pass rate (exec'd): 93.8%
Notes: All 7 failures = "Test terminated unexpectedly" on GB200 —
node instability, not product signal
────────────────────────────────────────
12
Test: test_w4_4gpus[v2_kv_cache-dp4-trtllm-auto]
Total: 121
Pass: 110
Fail: 11
Skip: 0
Pass rate (exec'd): 90.9%
Notes: All 11 failures = "Test terminated unexpectedly" on GB200 —
same GB200 infra pattern
────────────────────────────────────────
13
Test: test_bfloat16_4gpus[tp4-TRTLLM-compile=False]
Total: 125
Pass: 0
Fail: 0
Skip: 125
Pass rate (exec'd): n/a
Notes: Already 100% skipped in pre-merge (dead entry, safe to
relocate)
────────────────────────────────────────
14
Test: test_bfloat16_4gpus[pp4-TRTLLM-compile=False]
Total: 108
Pass: 0
Fail: 0
Skip: 108
Pass rate (exec'd): n/a
Notes: Already 100% skipped in pre-merge (dead entry, safe to
relocate)

Conclusion

All 14 tests are safe to move to post-merge. Two cuts strongly support this:

• Tests 1–9 (99–100% real pass rate): no product failures caught in pre-merge in the last week.
• Tests 10–12 (90–96% raw pass rate, but 100% product pass rate): every single failure is infra/environment noise, Ray import error or GB200 node crash. These tests have caught zero actual regressions; they've been adding CI-latency without adding signal.
• Tests 13–14: already always-skipped in pre-merge, so "moving them" is essentially cleanup.

Summary by CodeRabbit

• Tests
  • Reorganized GPU accuracy test configurations across multiple device types (H100, H200, GB200).
  • Shifted Llama 3.1 and GPT-OSS test cases between pre-merge and post-merge orchestration phases.
  • Updated test distribution across attention backend and compilation variants.

Description

Test Coverage

PR Checklist

Please review the following before submitting your PR:

• PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.

• PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

• Test cases are provided for new code paths (see test instructions)

• Any new dependencies have been scanned for license and vulnerabilities

• CODEOWNERS updated if ownership changes

• Documentation updated as needed

• Update tava architecture diagram if there is a significant design change in PR.

• The reviewers assigned automatically/manually are appropriate for the PR.

• Please check this after reviewing the above items as appropriate for this PR.

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[coderabbitai]

📝 Walkthrough

Walkthrough

Test configuration YAML files are reorganized to shift GPU-specific test cases between pre-merge and post-merge phases. Tests for models like Llama 3.1, GPT-OSS, and Qwen are repositioned across H100, H200, GB200, and B200 hardware configurations to adjust test scheduling and distribution across execution phases.

Changes

Cohort / File(s)	Summary
B200 Test Repositioning tests/integration/test_lists/test-db/l0_b200.yml	Relocates three PyTorch test variants (TestGPTOSS::test_w4_1gpu with trtllm-auto for both KV cache versions and TestQwen3_5_35B_A3B::test_bf16) to a later section of the test configuration without functional changes.
H100/H200 Test Adjustments tests/integration/test_lists/test-db/l0_dgx_h100.yml, tests/integration/test_lists/test-db/l0_dgx_h200.yml	Removes Llama 3.1 8B Instruct bfloat16 tests from H100 4-GPU suite (tp4 and tp2pp2 with TRTLLM backend) and adds corresponding test variants to H200 configuration with different torch_compile settings.
GB200 Multi-GPU Phase Shift tests/integration/test_lists/test-db/l0_gb200_multi_gpus.yml	Moves 4-GPU accuracy tests from pre_merge to post_merge phase: Llama 3.1 bfloat16 TP/PP variants (TRTLLM/FLASHINFER) and GPTOSS w4_4gpus cases with distributed training configurations.
H100 Pre/Post-Merge Reorganization tests/integration/test_lists/test-db/l0_h100.yml	Shifts Llama 3.1 8B Instruct bfloat16 TRTLLM tests from pre_merge MPI/PyTorch and Ray/PyTorch phases to post_merge MPI/PyTorch phase, adjusting torch_compile variant coverage.

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~10 minutes

🚥 Pre-merge checks | ✅ 5

✅ Passed checks (5 passed)

Check name	Status	Explanation
Title check	✅ Passed	The title clearly and concisely summarizes the main change: moving bf16/auto precision variants from pre-merge to post-merge test configuration.
Docstring Coverage	✅ Passed	No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Description check	✅ Passed	PR description clearly explains motivation, includes detailed risk evaluation with pass rate statistics, and provides measured pre-merge impact across multiple clusters.

_{✏️ Tip: You can configure your own custom pre-merge checks in the settings.}

✨ Finishing Touches

🧪 Generate unit tests (beta)

• Create PR with unit tests

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[QiJune]

/bot skip --comment "trivial changes"

[tensorrt-cicd]

PR_Github #45139 [ skip ] triggered by Bot. Commit: 5479371 Link to invocation

[tensorrt-cicd]

PR_Github #45139 [ skip ] completed with state SUCCESS. Commit: 5479371
Skipping testing for commit 5479371

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