[#13858][fix] AutoDeploy fix the piecewise vlm issue by nvchenghaoz · Pull Request #14006 · NVIDIA/TensorRT-LLM

nvchenghaoz · 2026-05-11T20:02:07Z

Enable the piecewise CG by default to see if there are any further errors.

The main fix is to move the Gamma related op to the dynamic split. Also update the kwargs capture to only capture the static related ones..

Summary by CodeRabbit

New Features
- Added support for Gemma4 multimodal mask preparation in CUDA graph compilation.
Improvements
- Optimized buffer allocation for captured graphs to allocate memory only for model parameters actually consumed by compiled submodules, reducing memory overhead.
Configuration Changes
- Enabled piecewise CUDA graph compilation by default.

Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

nvchenghaoz · 2026-05-11T20:03:10Z

/bot run --stage-list "DGX_B200-4_GPUs-AutoDeploy-1, DGX_H100-4_GPUs-AutoDeploy-1, DGX_H100-4_GPUs-AutoDeploy-Post-Merge-1,DGX_B200-8_GPUs-AutoDeploy-Post-Merge-1"

tensorrt-cicd · 2026-05-11T20:08:50Z

PR_Github #47790 [ run ] triggered by Bot. Commit: 9933fc6 Link to invocation

coderabbitai · 2026-05-11T20:10:31Z

📝 Walkthrough

Walkthrough

This PR enables piecewise CUDA graph compilation and optimizes static input buffer allocation in PiecewiseCapturedGraph by discovering which model-level kwargs are actually consumed by captured static runners and only allocating buffers for those specific kwargs, narrowing pre-allocation from all unstable kwargs to only those the runners use.

Changes

Static Input Buffer Filtering

Layer / File(s)	Summary
Configuration & Operation Registration `tensorrt_llm/_torch/auto_deploy/config/default.yaml`, `tensorrt_llm/_torch/auto_deploy/compile/piecewise_utils.py`	Enable `piecewise_enabled` in compile config. Register `auto_deploy::gemma4_prepare_multimodal_mask` as a metadata-prep dynamic op for graph splitting.
Static Runner Input Discovery `tensorrt_llm/_torch/auto_deploy/compile/backends/torch_cudagraph.py`	New `_static_runner_input_names()` method collects placeholder input names from each `ADPiecewiseRunner`'s FX graph and returns them as a set.
Buffer Allocation with Input Filtering `tensorrt_llm/_torch/auto_deploy/compile/backends/torch_cudagraph.py`	Update `_allocate_static_input_buffers()` to compute the static-runner-consumed input set, early-return if empty, and skip buffering unstable-address kwargs whose keys are not in that set.
Test Infrastructure & Validation `tests/unittest/auto_deploy/singlegpu/compile/test_captured_graph.py`, `tests/unittest/auto_deploy/singlegpu/compile/test_piecewise_utils.py`	Add `_add_static_runner_with_inputs()` helper to register minimal static runners. Update existing static-buffer test. Add new test verifying dynamic-only kwargs are skipped during allocation/copying. Add copyright update and import extension. Validate `gemma4_prepare_multimodal_mask` is classified as metadata-prep.

🎯 3 (Moderate) | ⏱️ ~20 minutes

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Description check	⚠️ Warning	The description addresses the main changes but lacks required template sections like Test Coverage and PR Checklist verification, making it incomplete according to the repository template.	Add the missing sections: Test Coverage (list relevant tests), and verify the PR Checklist items to meet the repository's contribution requirements.

✅ Passed checks (4 passed)

Check name	Status	Explanation
Title check	✅ Passed	The title clearly identifies the issue (`#13858`) and summarizes the fix for the piecewise VLM problem, directly reflecting the main changes in the changeset.
Docstring Coverage	✅ Passed	No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.

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⚠️ Outside diff range comments (1)

tensorrt_llm/_torch/auto_deploy/config/default.yaml (1)
302-308: ⚠️ Potential issue | 🔴 Critical

Enabling prototype piecewise CUDA graphs by default introduces stability and performance risks.

Piecewise CUDA graph support is marked as experimental/prototype in the codebase (commit #11422). The feature has documented issues including severe memory fragmentation in logits (mitigated via warmup requests) and recent bug fixes (nvbugs/5880745 for MoE compatibility, VLM issues). More critically, existing piecewise tests in CI are marked TIMEOUT, indicating correctness or performance problems that will now affect all deployments by default.

Before enabling this as the default, consider:

Piecewise support should remain opt-in until production-ready status

Investigate why existing piecewise tests timeout under B200 hardware

Validate that memory fragmentation mitigations work correctly across batch sizes

Add performance regression gates to prevent silent degradation
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@tensorrt_llm/_torch/auto_deploy/config/default.yaml` around lines 302 - 308,
The default config enables the experimental piecewise CUDA graphs
(compile_model.piecewise_enabled: true), which is unstable; change the default
to opt-in by setting compile_model.piecewise_enabled to false and leave
piecewise_num_tokens as null, update any related documentation or comments near
the compile_model block to indicate the feature is experimental and how to
enable it, and ensure any CI or deployment gating checks reference this opt-in
flag so piecewise remains disabled unless explicitly turned on.

🤖 Prompt for all review comments with AI agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Outside diff comments:
In `@tensorrt_llm/_torch/auto_deploy/config/default.yaml`:
- Around line 302-308: The default config enables the experimental piecewise
CUDA graphs (compile_model.piecewise_enabled: true), which is unstable; change
the default to opt-in by setting compile_model.piecewise_enabled to false and
leave piecewise_num_tokens as null, update any related documentation or comments
near the compile_model block to indicate the feature is experimental and how to
enable it, and ensure any CI or deployment gating checks reference this opt-in
flag so piecewise remains disabled unless explicitly turned on.

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📥 Commits

Reviewing files that changed from the base of the PR and between e197b69 and 9933fc6.

📒 Files selected for processing (5)

tensorrt_llm/_torch/auto_deploy/compile/backends/torch_cudagraph.py
tensorrt_llm/_torch/auto_deploy/compile/piecewise_utils.py
tensorrt_llm/_torch/auto_deploy/config/default.yaml
tests/unittest/auto_deploy/singlegpu/compile/test_captured_graph.py
tests/unittest/auto_deploy/singlegpu/compile/test_piecewise_utils.py

tensorrt-cicd · 2026-05-11T22:04:42Z

PR_Github #47790 [ run ] completed with state SUCCESS. Commit: 9933fc6
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Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

nvchenghaoz · 2026-05-12T00:09:49Z

/bot run --stage-list "A10-Build_Docs, A10-PackageSanityCheck-PY310-UB2204, A100X-PackageSanityCheck-PY312-UB2404, A30-AutoDeploy-1, H100_PCIe-AutoDeploy-1, DGX_B200-AutoDeploy-1, A100X-PyTorch-1, DGX_H100-4_GPUs-AutoDeploy-1, DGX_B200-4_GPUs-AutoDeploy-1, DGX_H100-4_GPUs-AutoDeploy-Post-Merge-1, DGX_B200-8_GPUs-AutoDeploy-Post-Merge-1"

tensorrt-cicd · 2026-05-12T00:17:39Z

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tensorrt-cicd · 2026-05-12T02:02:16Z

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suyoggupta · 2026-05-12T21:43:21Z

maybe we can try adding a smoke test https://sourcegraph.com/r/github.com/NVIDIA/TensorRT-LLM/-/blob/tests/unittest/auto_deploy/singlegpu/smoke/test_ad_build_small_single.py ?

…m_0511 Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com> # Conflicts: # tensorrt_llm/_torch/auto_deploy/compile/piecewise_utils.py # tests/unittest/auto_deploy/singlegpu/compile/test_piecewise_utils.py

nvchenghaoz · 2026-05-18T17:17:32Z

/bot run --stage-list "A10-Build_Docs, A10-PackageSanityCheck-PY310-UB2204, A100X-PackageSanityCheck-PY312-UB2404, A30-AutoDeploy-1, H100_PCIe-AutoDeploy-1, DGX_B200-AutoDeploy-1, A100X-PyTorch-1, DGX_H100-4_GPUs-AutoDeploy-1, DGX_B200-4_GPUs-AutoDeploy-1, DGX_H100-4_GPUs-AutoDeploy-Post-Merge-1, DGX_B200-8_GPUs-AutoDeploy-Post-Merge-1"

tensorrt-cicd · 2026-05-18T17:24:23Z

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nvchenghaoz · 2026-05-18T18:50:47Z

/bot run --stage-list "A10-Build_Docs, A10-PackageSanityCheck-PY310-UB2204, A100X-PackageSanityCheck-PY312-UB2404, A30-AutoDeploy-1, H100_PCIe-AutoDeploy-1, DGX_B200-AutoDeploy-1, A100X-PyTorch-1, DGX_H100-4_GPUs-AutoDeploy-1, DGX_B200-4_GPUs-AutoDeploy-1, DGX_H100-4_GPUs-AutoDeploy-Post-Merge-1, DGX_B200-8_GPUs-AutoDeploy-Post-Merge-1" --disable-fail-fast

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…m_0511 Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

…o chenghao/piecewise_vlm_0511 Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

nvchenghaoz · 2026-05-22T19:20:49Z

/bot run --stage-list "A10-Build_Docs, A10-PackageSanityCheck-PY310-UB2204, A100X-PackageSanityCheck-PY312-UB2404, A30-AutoDeploy-1, H100_PCIe-AutoDeploy-1, DGX_B200-AutoDeploy-1, A100X-PyTorch-1, DGX_H100-4_GPUs-AutoDeploy-1, DGX_B200-4_GPUs-AutoDeploy-1, DGX_H100-4_GPUs-AutoDeploy-Post-Merge-1, DGX_B200-8_GPUs-AutoDeploy-Post-Merge-1" --disable-fail-fast

tensorrt-cicd · 2026-05-22T19:27:18Z

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nvchenghaoz · 2026-05-23T02:36:49Z

/bot run --stage-list "A10-Build_Docs, A10-PackageSanityCheck-PY310-UB2204, A100X-PackageSanityCheck-PY312-UB2404, A30-AutoDeploy-1, H100_PCIe-AutoDeploy-1, DGX_B200-AutoDeploy-1, A100X-PyTorch-1, DGX_H100-4_GPUs-AutoDeploy-1, DGX_B200-4_GPUs-AutoDeploy-1, DGX_H100-4_GPUs-AutoDeploy-Post-Merge-1, DGX_B200-8_GPUs-AutoDeploy-Post-Merge-1" --disable-fail-fast

This reverts commit a75a643. Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

nvchenghaoz · 2026-06-01T16:36:00Z

/bot run --stage-list "A10-Build_Docs, A10-PackageSanityCheck-PY310-UB2204, A100X-PackageSanityCheck-PY312-UB2404, A30-AutoDeploy-1, H100_PCIe-AutoDeploy-1, DGX_B200-AutoDeploy-1, A100X-PyTorch-1, DGX_H100-4_GPUs-AutoDeploy-1, DGX_B200-4_GPUs-AutoDeploy-1, DGX_H100-4_GPUs-AutoDeploy-Post-Merge-1, DGX_B200-8_GPUs-AutoDeploy-Post-Merge-1" --disable-fail-fast

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…m_0511 Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com> # Conflicts: # tensorrt_llm/_torch/auto_deploy/compile/piecewise_utils.py

nvchenghaoz · 2026-06-02T16:34:32Z

/bot run --stage-list "A10-Build_Docs, A10-PackageSanityCheck-PY310-UB2204, A100X-PackageSanityCheck-PY312-UB2404, A30-AutoDeploy-1, H100_PCIe-AutoDeploy-1, DGX_B200-AutoDeploy-1, A100X-PyTorch-1, DGX_H100-4_GPUs-AutoDeploy-1, DGX_B200-4_GPUs-AutoDeploy-1, DGX_H100-4_GPUs-AutoDeploy-Post-Merge-1, DGX_B200-8_GPUs-AutoDeploy-Post-Merge-1" --disable-fail-fast

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fix the piecewise vlm issue

9933fc6

Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

nvchenghaoz requested a review from a team as a code owner May 11, 2026 20:02

nvchenghaoz requested a review from galagam May 11, 2026 20:02

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nvchenghaoz added 2 commits May 11, 2026 15:22

remove the lists to a more structured design for the dynamic ops

df90a69

Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

fix the trtllm error

5609e4a

Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

nvchenghaoz added 2 commits May 22, 2026 12:15

Merge remote-tracking branch 'origin/main' into chenghao/piecewise_vl…

c7efebf

…m_0511 Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

Merge remote-tracking branch 'origin/chenghao/piecewise_vlm_0511' int…

f408561

…o chenghao/piecewise_vlm_0511 Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

fix test failures

add6416

Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

nvchenghaoz requested a review from a team as a code owner May 23, 2026 02:36

suyoggupta approved these changes May 29, 2026

View reviewed changes

nvchenghaoz added 2 commits May 29, 2026 12:33

Revert "address reviewer's comment"

21eb9a7

This reverts commit a75a643. Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

add memory related tests for PCG

bfb4f70

Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

Merge remote-tracking branch 'origin/main' into chenghao/piecewise_vl…

cae8c0f

…m_0511 Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com> # Conflicts: # tensorrt_llm/_torch/auto_deploy/compile/piecewise_utils.py

nvchenghaoz added 2 commits June 10, 2026 11:05

Merge branch 'main' into chenghao/piecewise_vlm_0511

47bdac7

Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

support multi-pool for piecewise cudagraph

02d625e

Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

minor update

4b38a4d

Signed-off-by: Chenghao Zhang <211069071+nvchenghaoz@users.noreply.github.com>

nvchenghaoz enabled auto-merge (squash) June 11, 2026 04:20

nvchenghaoz merged commit 19b5d0e into NVIDIA:main Jun 11, 2026
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nvchenghaoz commented Jun 2, 2026

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tensorrt-cicd commented Jun 2, 2026

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tensorrt-cicd commented Jun 2, 2026

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nvchenghaoz commented Jun 10, 2026

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tensorrt-cicd commented Jun 10, 2026

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tensorrt-cicd commented Jun 10, 2026

Uh oh!

nvchenghaoz commented Jun 10, 2026

Uh oh!

tensorrt-cicd commented Jun 10, 2026

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tensorrt-cicd commented Jun 11, 2026

Uh oh!

nvchenghaoz commented Jun 11, 2026

nvchenghaoz commented May 11, 2026 •

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