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[https://nvbugs/6248837][fix] Densify trtllm-gen fmha warmup grid to catch missing kernels - #15305

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pengbowang-nv:dev-fix-update-warmup-grid
Jun 17, 2026
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[https://nvbugs/6248837][fix] Densify trtllm-gen fmha warmup grid to catch missing kernels#15305
pengbowang-nv merged 1 commit into
NVIDIA:mainfrom
pengbowang-nv:dev-fix-update-warmup-grid

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Description

Background and Analysis

After previous warmup modification PR at #14851 , most JIT in the middle of execution issue is resolved. However we met a problem on some particular DSR1 case, where a kernel is not covered in the warmup grid and cause performance issue afterwards. In this special case the kernel would be selected only if seqlen between a very narrow area (8193-9316).

This PR densified the grid based on learning from autotuner, and should protect this case and other possible narrow cases without introducing much overhead.

Why the soultion in this PR should work (even for future cases)

Given other parameters, the autotuner would select kernel based on batchSize, seqLenQ, seqLenKv. For decode case, seqLenQ is given. As attention is done in tiles, these parameters only affect autotuner by affecting number of total tile and tile per sequence.

When tile number is in the range of 1 - 24, the autotuner logic would be rather delicate so that we require dense cover of this area. Outside this area the autotuner logic will be much less delicate and we can just cover some of them.

Each tile can be of size 128, 256 and 512. The tile number per sequence is capped at multiprocessorCount and the total tile number also mostly work by comparing with multiprocessorCount multiplied by a factor.

So for seqLenKv we use such range: [*dense_tile_num_range, *sprase_tile_num_range] multiplied by [128, 256, 512]. dense_tile_num_range = [1,2, ..., 24] covers full 1-24 tile num range, and sparese_tile_num_range = [26, 28, 32, 40, 48, 64, 96, 128, 192, 256] would loosely cover from 24 - 256 (upper cap of multiprocessor count)

For batchsize we want total number of tiles cover 1 - 24 and loosely cover other cases. Remember we have full 1-24 tile for seqLenKv range, we would like to cover most cases for each seqLenKv (effectively tile number per sequence). For tileNumPerSeq = 1, we want batchsize = 1, ..., 24; for tileNumPerSeq = 2, we want batchsize = 1, ..., 12, etc. So the final coverage would be similar to tile range of seqLenKv, but I added more batchsizes just to be sure about real cases.

Overhead

As the warmup happens on C++ fmhaRunner level, the overhead would be much easier to handle. Overhead = Tuning Overhead + Kernel Compilation Overhead. For a given model config, as the warmup should catch every posssible kernel in the run, this can be seen as a constant. Before and after this PR this should not change much (it will increase as we did catch a previously missing kernel), likely an increase of 8s. And the Tuning Overhead = mesh point * tuning time * model layer number * number of execution, tuning time is typically less than 20us, interpreting to less than 6s for most models. In actual test environment the tuning overhead is measured less than 1s. I believe this is due to the fact we are overestimating the tuning time and mesh point.

Follow up tasks

  1. Change to tune only on a new layer, so we can remove model layer number factor from tuning overhead and allow for even more warmup.
  2. Reduce kernel compilation overhead.

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Summary by CodeRabbit

  • Refactor
    • Updated generation kernel warmup configuration to enhance compilation efficiency and provide optimized performance across various batch and sequence length scenarios.

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pengbowang-nv marked this pull request as ready for review June 16, 2026 06:02
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Review Change Stack

📝 Walkthrough

Walkthrough

In fmhaKernels.h, the JIT warmup grid candidate constants are replaced: the old combined Q/KV and prefill-specific batch vectors are removed and new separate default vectors for batch size, KV sequence length, and generation-kernel Q sequence length are introduced. The runJITWarmupGridIfRequested method is updated to always use these new vectors, with Q candidates switching on useGenKernelForPrefill.

Changes

JIT Warmup Grid Candidate Update

Layer / File(s) Summary
Warmup candidate constants and selection logic
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h
Removes prior default batch and combined Q/KV candidate vectors; adds new separate default vectors for batch size, KV sequence length, and gen-kernel Q sequence length (fixed 128). Updates runJITWarmupGridIfRequested to always draw batch from the unified default list, switch Q candidates based on useGenKernelForPrefill, and always draw KV candidates from the new KV list.

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~10 minutes

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (4 passed)
Check name Status Explanation
Title check ✅ Passed The title clearly summarizes the main change: densifying the FMHA warmup grid to catch missing kernels, directly addressing the performance issue described in the PR.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
Description check ✅ Passed The PR description provides comprehensive background, technical rationale, and analysis of the solution with detailed explanations of the warmup grid densification strategy and overhead estimates.

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🧹 Nitpick comments (1)
cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h (1)

304-326: 💤 Low value

Well-designed warmup grid candidates with clear rationale.

The new constant vectors provide good coverage based on autotuner sensitivity analysis. The comments clearly explain the selection strategy (dense coverage for tile counts 1-24, sparse coverage beyond).

Minor readability enhancement

Consider using digit separators for the larger literals to improve readability:

-        10752, 11264, 11776, 12288, 13312, 14336, 16384, 20480, 24576, 32768, 40960, 49152, 65536, 98304, 131072};
+        10'752, 11'264, 11'776, 12'288, 13'312, 14'336, 16'384, 20'480, 24'576, 32'768, 40'960, 49'152, 65'536, 98'304, 131'072};
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h` around lines
304 - 326, Add digit separators to improve readability of large numeric literals
in the warmup candidate vectors. Use C++ digit separator syntax (single quotes)
to separate groups of three digits in numbers within
kDefaultWarmupBatchSizeCandidates, kDefaultWarmupSeqLenKvCandidates, and
kDefaultWarmupSeqLenQCandidates constants. For example, replace numbers like
98304 with 98'304 and 131072 with 131'072 to make the large values easier to
read at a glance.
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Nitpick comments:
In `@cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h`:
- Around line 304-326: Add digit separators to improve readability of large
numeric literals in the warmup candidate vectors. Use C++ digit separator syntax
(single quotes) to separate groups of three digits in numbers within
kDefaultWarmupBatchSizeCandidates, kDefaultWarmupSeqLenKvCandidates, and
kDefaultWarmupSeqLenQCandidates constants. For example, replace numbers like
98304 with 98'304 and 131072 with 131'072 to make the large values easier to
read at a glance.

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📥 Commits

Reviewing files that changed from the base of the PR and between 130ae82 and 34fa064.

📒 Files selected for processing (1)
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/fmhaKernels.h

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pengbowang-nv requested review from yunruis and yuxianq June 16, 2026 06:46
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pengbowang-nv merged commit 7e24365 into NVIDIA:main Jun 17, 2026
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pengbowang-nv deleted the dev-fix-update-warmup-grid branch June 17, 2026 05:11
tensorrt-cicd added a commit to tensorrt-cicd/TensorRT-LLM that referenced this pull request Jun 17, 2026
…ngine configs

PR NVIDIA#14851 added a TRTLLM-Gen FMHA JIT warmup that enumerates a cartesian grid of
(batchSize, seqLenQ, seqLenKv) sized by the engine maxima, eagerly compiling
NVRTC kernels for each combo. PR NVIDIA#15305 then densified the candidate lists to
catch missing kernels. For long-context disagg configs such as
disagg_config_ctxtp2_gentp2_llama31_8b_ucx.yaml (max_num_requests=2048,
max_seq_len=131072), the densified grid contains thousands of points and the
NVRTC compilation time exceeds the 600s wait_for_disagg_server_ready timeout
in test_disaggregated_logprobs_serving[llama-3.1-8b-instruct].

Skip the warmup at the Python entry point when the engine maxima product would
produce a problematic grid. The runtime kernel selection path is unchanged --
any kernel that would have been warmed up will JIT-compile lazily on first
request instead. This restores the documented pre-PR NVIDIA#14851 behavior for
oversized configs without affecting the warmup benefit for regular configs.

Signed-off-by: tensorrt-cicd <90828364+tensorrt-cicd@users.noreply.github.com>
xinhe-nv pushed a commit to tensorrt-cicd/TensorRT-LLM that referenced this pull request Jun 23, 2026
…catch missing kernels (NVIDIA#15305)

Signed-off-by: Pengbo Wang <221450789+pengbowang-nv@users.noreply.github.com>
Signed-off-by: GitLab CI Bot <gitlab-ci@nvidia.com>
xinhe-nv pushed a commit to tensorrt-cicd/TensorRT-LLM that referenced this pull request Jun 24, 2026
…catch missing kernels (NVIDIA#15305)

Signed-off-by: Pengbo Wang <221450789+pengbowang-nv@users.noreply.github.com>
Signed-off-by: GitLab CI Bot <gitlab-ci@nvidia.com>
tensorrt-cicd added a commit to tensorrt-cicd/TensorRT-LLM that referenced this pull request Jun 24, 2026
…ngine configs

PR NVIDIA#14851 added a TRTLLM-Gen FMHA JIT warmup that enumerates a cartesian grid of
(batchSize, seqLenQ, seqLenKv) sized by the engine maxima, eagerly compiling
NVRTC kernels for each combo. PR NVIDIA#15305 then densified the candidate lists to
catch missing kernels. For long-context disagg configs such as
disagg_config_ctxtp2_gentp2_llama31_8b_ucx.yaml (max_num_requests=2048,
max_seq_len=131072), the densified grid contains thousands of points and the
NVRTC compilation time exceeds the 600s wait_for_disagg_server_ready timeout
in test_disaggregated_logprobs_serving[llama-3.1-8b-instruct].

Skip the warmup at the Python entry point when the engine maxima product would
produce a problematic grid. The runtime kernel selection path is unchanged --
any kernel that would have been warmed up will JIT-compile lazily on first
request instead. This restores the documented pre-PR NVIDIA#14851 behavior for
oversized configs without affecting the warmup benefit for regular configs.

Signed-off-by: tensorrt-cicd <90828364+tensorrt-cicd@users.noreply.github.com>
tensorrt-cicd added a commit to tensorrt-cicd/TensorRT-LLM that referenced this pull request Jun 26, 2026
…ngine configs

PR NVIDIA#14851 added a TRTLLM-Gen FMHA JIT warmup that enumerates a cartesian grid of
(batchSize, seqLenQ, seqLenKv) sized by the engine maxima, eagerly compiling
NVRTC kernels for each combo. PR NVIDIA#15305 then densified the candidate lists to
catch missing kernels. For long-context disagg configs such as
disagg_config_ctxtp2_gentp2_llama31_8b_ucx.yaml (max_num_requests=2048,
max_seq_len=131072), the densified grid contains thousands of points and the
NVRTC compilation time exceeds the 600s wait_for_disagg_server_ready timeout
in test_disaggregated_logprobs_serving[llama-3.1-8b-instruct].

Skip the warmup at the Python entry point when the engine maxima product would
produce a problematic grid. The runtime kernel selection path is unchanged --
any kernel that would have been warmed up will JIT-compile lazily on first
request instead. This restores the documented pre-PR NVIDIA#14851 behavior for
oversized configs without affecting the warmup benefit for regular configs.

Signed-off-by: tensorrt-cicd <90828364+tensorrt-cicd@users.noreply.github.com>
trtllm-agent pushed a commit to tensorrt-cicd/TensorRT-LLM that referenced this pull request Jul 7, 2026
…ngine configs

PR NVIDIA#14851 added a TRTLLM-Gen FMHA JIT warmup that enumerates a cartesian grid of
(batchSize, seqLenQ, seqLenKv) sized by the engine maxima, eagerly compiling
NVRTC kernels for each combo. PR NVIDIA#15305 then densified the candidate lists to
catch missing kernels. For long-context disagg configs such as
disagg_config_ctxtp2_gentp2_llama31_8b_ucx.yaml (max_num_requests=2048,
max_seq_len=131072), the densified grid contains thousands of points and the
NVRTC compilation time exceeds the 600s wait_for_disagg_server_ready timeout
in test_disaggregated_logprobs_serving[llama-3.1-8b-instruct].

Skip the warmup at the Python entry point when the engine maxima product would
produce a problematic grid. The runtime kernel selection path is unchanged --
any kernel that would have been warmed up will JIT-compile lazily on first
request instead. This restores the documented pre-PR NVIDIA#14851 behavior for
oversized configs without affecting the warmup benefit for regular configs.

Signed-off-by: tensorrt-cicd <90828364+tensorrt-cicd@users.noreply.github.com>
trtllm-agent pushed a commit to tensorrt-cicd/TensorRT-LLM that referenced this pull request Jul 13, 2026
…ngine configs

PR NVIDIA#14851 added a TRTLLM-Gen FMHA JIT warmup that enumerates a cartesian grid of
(batchSize, seqLenQ, seqLenKv) sized by the engine maxima, eagerly compiling
NVRTC kernels for each combo. PR NVIDIA#15305 then densified the candidate lists to
catch missing kernels. For long-context disagg configs such as
disagg_config_ctxtp2_gentp2_llama31_8b_ucx.yaml (max_num_requests=2048,
max_seq_len=131072), the densified grid contains thousands of points and the
NVRTC compilation time exceeds the 600s wait_for_disagg_server_ready timeout
in test_disaggregated_logprobs_serving[llama-3.1-8b-instruct].

Skip the warmup at the Python entry point when the engine maxima product would
produce a problematic grid. The runtime kernel selection path is unchanged --
any kernel that would have been warmed up will JIT-compile lazily on first
request instead. This restores the documented pre-PR NVIDIA#14851 behavior for
oversized configs without affecting the warmup benefit for regular configs.

Signed-off-by: tensorrt-cicd <90828364+tensorrt-cicd@users.noreply.github.com>
trtllm-agent pushed a commit to tensorrt-cicd/TensorRT-LLM that referenced this pull request Jul 15, 2026
…ngine configs

PR NVIDIA#14851 added a TRTLLM-Gen FMHA JIT warmup that enumerates a cartesian grid of
(batchSize, seqLenQ, seqLenKv) sized by the engine maxima, eagerly compiling
NVRTC kernels for each combo. PR NVIDIA#15305 then densified the candidate lists to
catch missing kernels. For long-context disagg configs such as
disagg_config_ctxtp2_gentp2_llama31_8b_ucx.yaml (max_num_requests=2048,
max_seq_len=131072), the densified grid contains thousands of points and the
NVRTC compilation time exceeds the 600s wait_for_disagg_server_ready timeout
in test_disaggregated_logprobs_serving[llama-3.1-8b-instruct].

Skip the warmup at the Python entry point when the engine maxima product would
produce a problematic grid. The runtime kernel selection path is unchanged --
any kernel that would have been warmed up will JIT-compile lazily on first
request instead. This restores the documented pre-PR NVIDIA#14851 behavior for
oversized configs without affecting the warmup benefit for regular configs.

Signed-off-by: tensorrt-cicd <90828364+tensorrt-cicd@users.noreply.github.com>
trtllm-agent pushed a commit to tensorrt-cicd/TensorRT-LLM that referenced this pull request Jul 16, 2026
…ngine configs

PR NVIDIA#14851 added a TRTLLM-Gen FMHA JIT warmup that enumerates a cartesian grid of
(batchSize, seqLenQ, seqLenKv) sized by the engine maxima, eagerly compiling
NVRTC kernels for each combo. PR NVIDIA#15305 then densified the candidate lists to
catch missing kernels. For long-context disagg configs such as
disagg_config_ctxtp2_gentp2_llama31_8b_ucx.yaml (max_num_requests=2048,
max_seq_len=131072), the densified grid contains thousands of points and the
NVRTC compilation time exceeds the 600s wait_for_disagg_server_ready timeout
in test_disaggregated_logprobs_serving[llama-3.1-8b-instruct].

Skip the warmup at the Python entry point when the engine maxima product would
produce a problematic grid. The runtime kernel selection path is unchanged --
any kernel that would have been warmed up will JIT-compile lazily on first
request instead. This restores the documented pre-PR NVIDIA#14851 behavior for
oversized configs without affecting the warmup benefit for regular configs.

Signed-off-by: tensorrt-cicd <90828364+tensorrt-cicd@users.noreply.github.com>
trtllm-agent pushed a commit to tensorrt-cicd/TensorRT-LLM that referenced this pull request Jul 17, 2026
…ngine configs

PR NVIDIA#14851 added a TRTLLM-Gen FMHA JIT warmup that enumerates a cartesian grid of
(batchSize, seqLenQ, seqLenKv) sized by the engine maxima, eagerly compiling
NVRTC kernels for each combo. PR NVIDIA#15305 then densified the candidate lists to
catch missing kernels. For long-context disagg configs such as
disagg_config_ctxtp2_gentp2_llama31_8b_ucx.yaml (max_num_requests=2048,
max_seq_len=131072), the densified grid contains thousands of points and the
NVRTC compilation time exceeds the 600s wait_for_disagg_server_ready timeout
in test_disaggregated_logprobs_serving[llama-3.1-8b-instruct].

Skip the warmup at the Python entry point when the engine maxima product would
produce a problematic grid. The runtime kernel selection path is unchanged --
any kernel that would have been warmed up will JIT-compile lazily on first
request instead. This restores the documented pre-PR NVIDIA#14851 behavior for
oversized configs without affecting the warmup benefit for regular configs.

Signed-off-by: tensorrt-cicd <90828364+tensorrt-cicd@users.noreply.github.com>
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