[TRTLLM-12807][feat] Wrap CuteDSL MLA decode as FMHA lib - #15333
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Add a CuteDSL attention backend that intercepts the MLA decode-only path
and dispatches to Blackwell CuTe DSL kernels (FP8 e4m3 / FP16), falling
back to TrtllmAttention for all other paths.
- attention_backend/cute_dsl.py: CuteDslAttention(TrtllmAttention)
- cute_dsl_kernels/blackwell/attention/mla: decode fp8/fp16 kernels + helpers
- custom_ops: register cute_dsl_mla_decode_{fp8,fp16}_blackwell ops
- utils/__init__: wire up CUTEDSL backend selection
- tests: CUTEDSL coverage in test_attention_mla + dedicated decode test
Signed-off-by: haow <haow@nvidia.com>
…ayer paged-KV, multi-layer test - attention_backend/cute_dsl.py: feed the scaled quant_q_buffer (not q.to(fp8)) and fold the fp8 dequant + de-folded log2(e) softmax scale into the bmm1/bmm2 scales; resolve the per-layer KV pool / page-table for layer_idx>0; gate the non-causal fast path off CUSTOM masks and speculative decoding; add a once-per-process ENGAGED log (symmetric to the fallback warning) confirming the decode kernel actually ran. - custom_ops/cute_dsl_custom_ops.py: add BF16 to the decode runner and the fp16 op with dtype dispatch + validation; pass workspace=None for split_kv==1 to avoid a zero-sized-buffer global write. - cute_dsl_kernels/.../mla_decode_fp8.py: allow a widened BF16 attention output. - cute_dsl_kernels/.../mla_decode_fp16.py: accept BF16 input/output in can_implement. - tests/.../test_cute_dsl_mla_decode.py: parametrize over num_layers to exercise the layer_idx>0 paged-KV path (reproduces the real DeepSeek-V3 E2E case). Signed-off-by: haow <haow@nvidia.com>
…fp8 scale Normalize the per-layer paged-KV pool view for the v1 KVCacheManager (interleaved single-pool layout) to a packed combined-slot view and fold the layer offset into the page table, so the CuTe DSL paged TMA addresses the correct layer's memory. No-op for the v2 manager. Cache the static fp8 dequant scales on the per-layer backend instance and read them eagerly during warmup, avoiding an illegal .item() device->host sync under CUDA graph capture. Add a long decode-only test that crosses paged-KV block boundaries mid-decode (short prompt, 64 steps), parametrized over v1/v2 KV cache managers, reproducing the DeepSeek-V3 E2E degeneration path. Signed-off-by: haow <haow@nvidia.com>
Signed-off-by: Yuxian Qiu <142763828+yuxianq@users.noreply.github.com>
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This PR's commit has been cherry-picked to target branch in #15138, close it |
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@coderabbitai summary
Description
Wrap the CuteDSL FP8/FP16 MLA decode kernels as a TRTLLM FMHA library so they participate in the new FMHA library selection path.
This PR:
tensorrt_llm/_torch/attention_backend/fmha/.cute_dsl_mlainFMHA_LIBS.TLLM_FMHA_LIBSordering.generation_seq_len_q=[1, 4]coverage by replaying the single-token CuteDSL kernel per intra-step query with adjusted effective KV lengths.Test Coverage
B200:
python3 -m pytest -p no:threadleak -q tests/unittest/_torch/attention/test_cute_dsl_mla_decode.py --timeout=600 --tb=short(16 passed)python3 -m pytest -p no:threadleak -q tests/unittest/_torch/attention/test_attention_mla.py --timeout=600 --tb=short(87 passed)Local:
python3 -m py_compile tensorrt_llm/_torch/attention_backend/fmha/cute_dsl.py tests/unittest/_torch/attention/test_cute_dsl_mla_decode.py tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.pyruff check --config ruff-legacy.toml tensorrt_llm/_torch/attention_backend/fmha/cute_dsl.py tests/unittest/_torch/attention/test_cute_dsl_mla_decode.py tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.pygit diff --checkPR Checklist
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