[https://nvbugs/6316981][test] unwaive AutoDeploy SuperV3 MTP tests

[govind-ramnarayan]

The failure tracked by nvbug 6316981 was caused by piecewise CUDA graph being applied to SuperV3 + MTP, which MTP does not support.

This is now disabled via piecewise_enabled: false in super_v3_mtp.yaml, so MTP runs the monolithic cudagraph path with the overlap scheduler on. See: #15325

Verified TestNemotronSuperV3::test_mtp[fp8_ws4_80gb-trtllm] on B200: GSM8K 92.76 (ref 92.10), spec-dec acceptance 52.78% (>0.40 threshold). Unwaive the GB200 and GB300 entries that share this root cause.

There is no 4xB200 PostMerge entry for AutoDeploy currently enabled, so we cannot test this with PostMerge. We tested manually on 4xB200. The bf16 and nvfp4 tests still failed during cudagraph capture, but are fixed by disabling SSM replay. See: #15565

Summary by CodeRabbit

• Chores
  • Updated integration test waive configurations for GB200 and GB300 hardware setups. Modified which tests are waived to align with current testing requirements.

Description

Test Coverage

PR Checklist

Please review the following before submitting your PR:

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[coderabbitai]

📝 Walkthrough

Walkthrough

Updates tests/integration/test_lists/waives.txt to remove a GB200 waiver for TestNemotronSuperV3::test_mtp[fp8_ws4_80gb-trtllm] and add new GB200 waivers for three Qwen3/Qwen2.5-VL tests and two GB300 waivers for Llama3.1 and NemotronNanoV3 tests.

Changes

Integration Test Waiver Updates

Layer / File(s)	Summary
GB200/GB300 waiver entry replacements tests/integration/test_lists/waives.txt	Removes the GB200 waiver for TestNemotronSuperV3::test_mtp[fp8_ws4_80gb-trtllm] and adds GB200 waivers for TestQwen3NextThinking::test_auto_dtype[tp4ep4], TestQwen3_5_35B_A3B::test_fp8_moe_dflash, and TestQwen2_5_VL_7B::test_auto_dtype, plus GB300 waivers for TestLlama3_1_8BInstruct::test_auto_dtype[True-False-False-False] and TestNemotronNanoV3::test_accuracy[nvfp4-1-attn_dp_off-trtllm].

Estimated code review effort

🎯 1 (Trivial) | ⏱️ ~2 minutes

Possibly related PRs

• NVIDIA/TensorRT-LLM#15505: Updates the same waives.txt file with overlapping entries for TestQwen2_5_VL_7B::test_auto_dtype on B200/GB200 configurations.
• NVIDIA/TensorRT-LLM#15506: Directly edits waives.txt adjusting the same entries including TestNemotronSuperV3::test_mtp[fp8_ws4_80gb-trtllm], TestQwen3_5_35B_A3B::test_fp8_moe_dflash, and TestQwen2_5_VL_7B::test_auto_dtype.
• NVIDIA/TensorRT-LLM#15535: Edits waives.txt with overlapping waivers for TestQwen3_5_35B_A3B and other Nemotron-related entries.

Suggested reviewers

• crazydemo
• jieli-matrix
• LarryXFly
• StanleySun639
• xinhe-nv

🚥 Pre-merge checks | ✅ 3 | ❌ 2

❌ Failed checks (2 warnings)

Check name	Status	Explanation	Resolution
Title check	⚠️ Warning	The title references unwaiving SuperV3 MTP tests, but the actual changes remove a GB200 waive and add new waives for unrelated test cases, which is the opposite of what the title claims.	Update the title to accurately reflect that the PR removes one waive and adds multiple new waives for different test cases (e.g., 'Update integration test waives for GB200/GB300 configurations').
Description check	⚠️ Warning	The PR description is incomplete and does not follow the required template structure.	Add proper PR title with ticket format, fill Description and Test Coverage sections, and ensure all PR Checklist items are addressed appropriately.

✅ Passed checks (3 passed)

Check name	Status	Explanation
Docstring Coverage	✅ Passed	No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.

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✨ Finishing Touches

🧪 Generate unit tests (beta)

• Create PR with unit tests

---

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[govind-ramnarayan]

Ran fp8 test locally on a B200 to confirm:

[06/23/2026-15:13:15] [TRT-LLM] [I] [evaluate] lm-eval gsm8k average accuracy: 92.76
[06/23/2026-15:13:15] [TRT-LLM] [I] Hypothesis testing report:
===========================================================
= ACCURACY HYPOTHESIS TESTING
===========================================================
Alpha (Type I:  False Positive): 0.050
Beta  (Type II: False Negative): 0.200
Sigma (Standard deviation): 50.000
#Samples: 1319
Higher is better: True
Theta (Minimum detectable effect): 4.841
Reference accuracy: 92.610
Threshold: 89.407
===========================================================
Evaluated accuracy: 92.760
===========================================================
Spec dec acceptance rate: 52.78% (24151/45756 tokens across 1001 speculative iterations)

[govind-ramnarayan]

/bot run --stage-list "DGX_H100-4_GPUs-AutoDeploy-1"

[tensorrt-cicd]

PR_Github #55363 [ run ] triggered by Bot. Commit: 414a3d9 Link to invocation

[tensorrt-cicd]

PR_Github #55363 [ run ] completed with state FAILURE. Commit: 414a3d9
/LLM/main/L0_MergeRequest_PR pipeline #44312 (Partly Tested) completed with status: 'FAILURE'

CI Report

⚠️ Action Required:

• Please check the failed tests and fix your PR
• If you cannot view the failures, ask the CI triggerer to share details
• Once fixed, request an NVIDIA team member to trigger CI again

CI Agent Failure Analysis

Link to invocation

[govind-ramnarayan]

/bot run

[govind-ramnarayan]

/bot run

[tensorrt-cicd]

PR_Github #55549 [ run ] triggered by Bot. Commit: 0841808 Link to invocation

[tensorrt-cicd]

PR_Github #55549 [ run ] completed with state FAILURE. Commit: 0841808
/LLM/main/L0_MergeRequest_PR pipeline #44471 completed with status: 'FAILURE'

CI Report

⚠️ Action Required:

• Please check the failed tests and fix your PR
• If you cannot view the failures, ask the CI triggerer to share details
• Once fixed, request an NVIDIA team member to trigger CI again

CI Agent Failure Analysis

Link to invocation

[tburt-nv]

/bot run --disable-fail-fast

[govind-ramnarayan]

Closed; better solution that fixes SSM replay for AutoDeploy is in #15622