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[https://nvbugs/6404567][fix] Clamp piecewise cudagraph captures to the reachable ceiling instead of force-appending it - #16256

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dongfengy:user/dongfengy/nvbug6404567-piecewise-clamp
Jul 17, 2026
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[https://nvbugs/6404567][fix] Clamp piecewise cudagraph captures to the reachable ceiling instead of force-appending it#16256
dongfengy merged 1 commit into
NVIDIA:mainfrom
dongfengy:user/dongfengy/nvbug6404567-piecewise-clamp

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@dongfengy dongfengy commented Jul 10, 2026

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Summary by CodeRabbit

  • Bug Fixes

    • Improved piecewise CUDA graph capture handling when requested token limits exceed the reachable ceiling.
    • Candidate values are now clamped appropriately without adding unrequested capture sizes.
    • Updated warnings to clearly explain clamping and how to enable larger graphs.
  • Tests

    • Added regression coverage to ensure distant ceiling values are not added unexpectedly.
    • Updated expectations for token limits and candidate filtering behavior.

Description

PR #13574 fixed https://nvbugs/5615248 by (a) dropping piecewise CUDA-graph capture candidates above the reachable ceiling max_batch_size*(max_seq_len-1-num_extra_decoding_steps) and (b) force-appending the ceiling itself to the capture list.

(b) causes a serving perf regression (https://nvbugs/6404567, first shipped in 1.3.0rc15, still present on main): runtime padding rounds each context-bearing iteration up to the nearest captured size, so appending a far ceiling — 65536 over a user capture_num_tokens list topping at 13914 in the gpt-oss-120b GB300 serving config — makes every (13914, 65536]-token iteration execute the full 65536-token graph. Measured per-iteration device time is flat ~325-400 ms vs 116-408 ms true-size eager (up to 2.8x), which serializes all in-flight decode streams behind those iterations: -12% QPS, TTFT more than doubles at high concurrency.

This PR replaces drop-and-append with clamping: user-requested sizes above the reachable ceiling are lowered to the ceiling (a requested 128 becomes 127 when only 127 is recordable — the resulting capture list for the 5615248 config is preserved bit-for-bit), and no capture size beyond the user's list is ever invented. Configs without oversized entries keep exactly their own capture list, i.e. pre-1.3.0rc15 behavior.

Validation (GB300, gpt-oss-120b, production serving config from the bug, 4x TP1 servers, 896 concurrent streams/server, 24000 requests per arm, steady-window aggregates):

Arm QPS TPOT
1.3.0rc14 (last good) 51.40 55.4 ms
rc15 / rc17 / rc18 / rc20 / main stock (65536 capture present) 44.3-44.7 64-65 ms
rc15 / rc18 / rc20 + this fix 51.6-52.3 ~55 ms
main + this fix, same-binary A/B vs main stock 52.15 vs 44.63 54.4 vs 64.5 ms

The main A/B used one build (identical native library SHAs in both arms' manifests); only the Python delta of this commit differs.

Test Coverage

  • tests/unittest/llmapi/test_llm_args.py::TestPiecewiseCudaGraphCaptureDefaults: 2 new tests (a far ceiling is never invented — the exact 6404567 shape; multiple oversized candidates collapse to the clamped ceiling), 3 existing tests updated to the clamp semantics, and the NVBugs 5615248 regression tests pass unchanged (128 is clamped to 127 instead of dropped+re-appended, producing the same list). 13/13 selected tests pass.
  • End-to-end A/B on GB300 as described above.

PR Checklist

Please review the following before submitting your PR:

  • PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.

  • PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

  • Test cases are provided for new code paths (see test instructions)

  • If PR introduces API changes, an appropriate PR label is added - either api-compatible or api-breaking. For api-breaking, include BREAKING in the PR title.

  • Any new dependencies have been scanned for license and vulnerabilities

  • CODEOWNERS updated if ownership changes

  • Documentation updated as needed

  • Update tava architecture diagram if there is a significant design change in PR.

  • The reviewers assigned automatically/manually are appropriate for the PR.

  • Please check this after reviewing the above items as appropriate for this PR.

🤖 Generated with Claude Code

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dongfengy requested a review from a team as a code owner July 10, 2026 22:51
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dongfengy requested a review from joyang-nv July 10, 2026 22:51
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Review Change Stack

📝 Walkthrough

Walkthrough

Piecewise CUDA graph capture filtering now clamps requested sizes to the reachable ceiling without appending unrequested ceiling values. Warmup warnings and unit tests were updated to reflect the revised behavior.

Changes

Piecewise capture ceiling clamping

Layer / File(s) Summary
Clamp capture candidates to the reachable ceiling
tensorrt_llm/_torch/pyexecutor/model_engine.py
The filter clamps user-provided capture sizes to the reachable ceiling, and the warmup warning describes the clamping behavior.
Validate candidate preservation and clamping
tests/unittest/llmapi/test_llm_args.py
Tests verify that far ceiling values are not appended, small candidate lists remain unchanged, and ceiling-derived expectations use the revised value.

Estimated code review effort: 3 (Moderate) | ~20 minutes

🚥 Pre-merge checks | ✅ 5
✅ Passed checks (5 passed)
Check name Status Explanation
Title check ✅ Passed The title matches the main change and follows the repository's ticket/type/summary template.
Description check ✅ Passed The description includes the required Description, Test Coverage, and PR Checklist sections with substantive details.
Docstring Coverage ✅ Passed No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
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dongfengy requested a review from brb-nv July 10, 2026 22:55

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Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (1)
tensorrt_llm/_torch/pyexecutor/model_engine.py (1)

479-485: 📐 Maintainability & Code Quality | 🟡 Minor | ⚡ Quick win

Warning text contradicts the new clamping behavior.

The message still opens with "Skipping piecewise CUDA graph capture for num_tokens=..." but the revised logic no longer skips these sizes — they are clamped down to the reachable ceiling and a graph is still captured there. The trailing "Clamping them to the ceiling" conflicts with the leading "Skipping", which will read as contradictory to operators triaging logs.

📝 Suggested wording
         if unrecordable:
             logger.warning(
-                f"Skipping piecewise CUDA graph capture for num_tokens="
-                f"{unrecordable}: exceeds reachable ceiling "
+                f"Piecewise CUDA graph capture requested for num_tokens="
+                f"{unrecordable} exceeds reachable ceiling "
                 f"max_batch_size*(max_seq_len-1-num_extra_decoding_steps)="
                 f"{max(0, self.batch_size * (self.max_seq_len - 1 - num_extra_decoding_steps))}. "
                 f"Clamping them to the ceiling; raise max_seq_len for larger graphs."
             )
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@tensorrt_llm/_torch/pyexecutor/model_engine.py` around lines 479 - 485,
Update the warning in the piecewise CUDA graph capture logic to describe
clamping rather than skipping: revise the message in the relevant capture path
to state that the unrecordable token sizes are clamped to the reachable ceiling
and captured at that ceiling, while retaining the ceiling calculation and
guidance to increase max_seq_len.
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Outside diff comments:
In `@tensorrt_llm/_torch/pyexecutor/model_engine.py`:
- Around line 479-485: Update the warning in the piecewise CUDA graph capture
logic to describe clamping rather than skipping: revise the message in the
relevant capture path to state that the unrecordable token sizes are clamped to
the reachable ceiling and captured at that ceiling, while retaining the ceiling
calculation and guidance to increase max_seq_len.

ℹ️ Review info
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Configuration used: Path: .coderabbit.yaml

Review profile: CHILL

Plan: Enterprise

Run ID: 218b23e5-f7fa-4a70-86c3-0ac33f149f52

📥 Commits

Reviewing files that changed from the base of the PR and between 2cbdaa0 and ed4ad61.

📒 Files selected for processing (2)
  • tensorrt_llm/_torch/pyexecutor/model_engine.py
  • tests/unittest/llmapi/test_llm_args.py

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dongfengy force-pushed the user/dongfengy/nvbug6404567-piecewise-clamp branch from ed4ad61 to cf25857 Compare July 14, 2026 23:55
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…he reachable ceiling instead of force-appending it

_filter_piecewise_capture_num_tokens force-appended the reachable
ceiling (min(max_num_tokens, max_batch_size*(max_seq_len-1))) to the
piecewise capture list whenever the user's largest entry was below it.
Runtime padding rounds each iteration up to the nearest captured size,
so a far appended ceiling (65536 over a user list topping at 13914)
made every (13914, 65536]-token iteration execute the full 65536-token
graph: up to ~2.8x device time on those iterations, -12% QPS / +146%
TTFT on gpt-oss-120b GB300 IFB serving (the rc14->rc15 regression).

Replace drop-and-append with clamping: user-requested sizes above the
reachable ceiling are lowered to the ceiling (a requested 128 becomes
127 when only 127 is recordable, preserving the NVBug 5615248 fix
bit-for-bit), and no capture size beyond the user's list is ever
invented. Configs without oversized entries keep exactly their own
capture list, i.e. pre-rc15 behavior.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Signed-off-by: Dongfeng Yu <dongfengy@nvidia.com>
@dongfengy
dongfengy force-pushed the user/dongfengy/nvbug6404567-piecewise-clamp branch from cf25857 to 7e4069f Compare July 15, 2026 00:01
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Thank you for looking into this!

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dongfengy merged commit 459839c into NVIDIA:main Jul 17, 2026
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