[https://nvbugs/6481375][test] Unwaive passing DSV3-Lite tests

[lfr-0531]

Description

Remove three stale DSV3-Lite test waivers after validating the corresponding
configurations on GitHub main:

• NVBug 6481375: unwaive the 4-GPU disaggregated gen-first test after the
  rank-aware KV cache V2 host-tier sizing fix in [None][fix] Make auto host tier sizing rank-aware in KVCacheManagerV2 #16106.
• NVBug 6400067: unwaive the GB200 DSV3-Lite tests with KV cache V2 both
  disabled and enabled after the CUDA graph attention workspace fix in [None][fix] avoid attention workspace resize during CUDA graph capture #16319.
• Keep the 8-GPU RTX PRO 6000 waiver for NVBug 6400067 because that hardware
  configuration was not available on the B200 validation host.

The two GB200 waiver removals for NVBug 6400067 overlap with #16441. They are
retained in this draft so the branch records the validation performed for both
NVBugs and can be adjusted depending on which PR lands first.

Test Coverage

Validated on GitHub main at f20ea652dd621006148aa918c970ba686cdda407.
The runtime source and compiled bindings were verified to resolve from this
worktree before running the tests.

• tests/integration/defs/accuracy/test_disaggregated_serving.py::TestDeepSeekV3Lite::test_gen_first[noadp-mtp0]
  (1 passed, 548.57s)
• tests/integration/defs/accuracy/test_llm_api_pytorch.py::TestDeepSeekV3Lite::test_bfloat16[mtp_nextn=2-attention_dp=True-cuda_graph=True-overlap_scheduler=True-torch_compile=True-enable_chunked_prefill=True-v2_kv_cache=False]
  (1 passed, 598.69s)
• tests/integration/defs/accuracy/test_llm_api_pytorch.py::TestDeepSeekV3Lite::test_bfloat16[mtp_nextn=2-attention_dp=True-cuda_graph=True-overlap_scheduler=True-torch_compile=True-enable_chunked_prefill=True-v2_kv_cache=True]
  (1 passed, 667.57s)
• pytest -q tests/unittest/_torch/executor/test_kvv2_host_tier_sizing.py
  (8 passed)
• pre-commit run --files tests/integration/test_lists/waives.txt

PR Checklist

Please review the following before submitting your PR:

• PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.

• PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

• Test cases are provided for new code paths (see test instructions)

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• Any new dependencies have been scanned for license and vulnerabilities

• CODEOWNERS updated if ownership changes

• Documentation updated as needed

• Update tava architecture diagram if there is a significant design change in PR.

• The reviewers assigned automatically/manually are appropriate for the PR.

• Please check this after reviewing the above items as appropriate for this PR.

GitHub Bot Help

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[lfr-0531]

/bot run --disable-fail-fast

[tensorrt-cicd]

PR_Github #62659 [ run ] triggered by Bot. Commit: 2f7c87d Link to invocation

[tensorrt-cicd]

PR_Github #62659 [ run ] completed with state SUCCESS. Commit: 2f7c87d
/LLM/main/L0_MergeRequest_PR pipeline #50799 completed with status: 'SUCCESS'

CI Report

Link to invocation