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[TRTLLM-7263][fix] Prevent recreation of cublas handles in lora_grouped_gemm every call#7053

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[TRTLLM-7263][fix] Prevent recreation of cublas handles in lora_grouped_gemm every call#7053
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@amitz-nv amitz-nv commented Aug 19, 2025

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Cherrypick of merge commit of #6968

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Summary by CodeRabbit

  • Refactor
    • Optimized LoRA grouped GEMM execution with thread-local, lazy initialization of GPU compute resources, reducing per-call overhead.
    • Improves latency and throughput, especially under multi-threaded workloads.
    • Enhances stability by avoiding repeated initialization in concurrent scenarios.
    • Minor naming consistency cleanup for maintainability.

…ed_gemm every call (NVIDIA#6968)

Signed-off-by: Amit Zuker <203509407+amitz-nv@users.noreply.github.com>
@amitz-nv amitz-nv self-assigned this Aug 19, 2025
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amitz-nv requested a review from a team as a code owner August 19, 2025 14:45
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📝 Walkthrough

Walkthrough

Thread-local, lazy initialization of CublasMMWrapper is introduced in lora_grouped_gemm. A thread_local std::shared_ptr is created on first use via getCublasHandle and getCublasLtHandle, and then reused. Variable name corrected to cublasWrapper. Applied to both constructor sites for LoraImpl.

Changes

Cohort / File(s) Summary
Thread-local CublasMMWrapper init in LoRA op
cpp/tensorrt_llm/thop/loraOp.cpp
Replace per-call CublasMMWrapper creation with thread_local, lazily-initialized shared_ptr; initialize on first use with getCublasHandle/getCublasLtHandle; use cublasWrapper for LoraImpl construction in both call sites; fix variable name typo.

Sequence Diagram(s)

sequenceDiagram
  autonumber
  participant Caller
  participant lora_grouped_gemm
  participant TLS as thread_local cublasWrapper
  participant CUDA as getCublasHandle/getCublasLtHandle
  participant Lora as LoraImpl

  Caller->>lora_grouped_gemm: invoke(...)
  alt cublasWrapper not initialized in this thread
    lora_grouped_gemm->>TLS: check cublasWrapper
    lora_grouped_gemm->>CUDA: getCublasHandle(), getCublasLtHandle()
    CUDA-->>lora_grouped_gemm: handles
    lora_grouped_gemm->>TLS: create and store CublasMMWrapper
    Note right of TLS: Lazy init per thread
  else already initialized
    lora_grouped_gemm->>TLS: reuse cublasWrapper
  end
  lora_grouped_gemm->>Lora: construct LoraImpl(cublasWrapper)
  Lora-->>Caller: perform GEMM (LoRA grouped)
  Note over lora_grouped_gemm,Lora: Subsequent calls reuse wrapper in the same thread
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Estimated code review effort

🎯 2 (Simple) | ⏱️ ~10 minutes

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  • shaharmor98

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Actionable comments posted: 0

🧹 Nitpick comments (2)
cpp/tensorrt_llm/thop/loraOp.cpp (2)

133-140: Thread-local lazy init: good improvement; add device guard and align with static naming convention

Great call moving to thread-local lazy initialization to avoid per-call handle churn. Two follow-ups:

  • Guard against device switches on the same thread (e.g., multi-GPU scenarios) so cached handles always match the current device.
  • Per guidelines, locally visible statics should use sPrefix; also mark locals const when not modified.

Proposed change:

-thread_local std::shared_ptr<tensorrt_llm::common::CublasMMWrapper> cublasWrapper;
-if (cublasWrapper == nullptr)
-{
-    auto cublasHandle = getCublasHandle();
-    auto cublasLtHandle = getCublasLtHandle();
-    cublasWrapper
-        = std::make_shared<tensorrt_llm::common::CublasMMWrapper>(cublasHandle, cublasLtHandle, nullptr, nullptr);
-}
+thread_local int sCublasWrapperDevice = -1;
+thread_local std::shared_ptr<tensorrt_llm::common::CublasMMWrapper> sCublasWrapper;
+int const currentDevice = at::cuda::current_device();
+if (!sCublasWrapper || sCublasWrapperDevice != currentDevice)
+{
+    auto const cublasHandle = getCublasHandle();
+    auto const cublasLtHandle = getCublasLtHandle();
+    sCublasWrapper = std::make_shared<tensorrt_llm::common::CublasMMWrapper>(
+        cublasHandle, cublasLtHandle, nullptr, nullptr);
+    sCublasWrapperDevice = currentDevice;
+}

Notes:

  • This keeps behavior identical for single-device runs while making it device-aware.
  • Confirm availability/semantics of at::cuda::current_device() in your PyTorch version; if your getCublasHandle/getCublasLtHandle are already per-device/thread and safe across device switches, we can skip the guard.

Also, it’s good that you did not add setStream() here; as learned in prior PRs, LoraImpl::run() handles setStream()/setWorkspace internally in _runGemm().

If you want, I can factor this into a small helper (e.g., getThreadLocalCublasWrapper()) and update call sites.


158-158: Pass the renamed thread-local wrapper variable at construction (if you adopt the sPrefix change)

Update the argument to use sCublasWrapper to match the suggested rename above:

-    auto mLoraImpl = std::make_shared<tensorrt_llm::kernels::LoraImpl>(
-        inHiddenSize, outHiddenSizes, transA, transB, numLoraModules, loraRuntimeDataType, max_low_rank, cublasWrapper);
+    auto mLoraImpl = std::make_shared<tensorrt_llm::kernels::LoraImpl>(
+        inHiddenSize, outHiddenSizes, transA, transB, numLoraModules, loraRuntimeDataType, max_low_rank, sCublasWrapper);
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🧠 Learnings (2)
📚 Learning: 2025-08-17T15:07:01.380Z
Learnt from: amitz-nv
PR: NVIDIA/TensorRT-LLM#6968
File: cpp/tensorrt_llm/thop/loraOp.cpp:133-141
Timestamp: 2025-08-17T15:07:01.380Z
Learning: In TensorRT-LLM's LoRA implementation, the LoraImpl::run() method handles setStream() internally in _runGemm(), along with setWorkspace(). Both stream and workspace are passed as arguments to run(), so there's no need to call setStream() explicitly in loraOp.cpp - this avoids redundancy and follows the intended architectural separation.

Applied to files:

  • cpp/tensorrt_llm/thop/loraOp.cpp
📚 Learning: 2025-08-17T15:07:01.380Z
Learnt from: amitz-nv
PR: NVIDIA/TensorRT-LLM#6968
File: cpp/tensorrt_llm/thop/loraOp.cpp:133-141
Timestamp: 2025-08-17T15:07:01.380Z
Learning: In TensorRT-LLM's LoRA implementation, the LoraImpl::run() method handles setStream() internally in _runGemm() (line 51 in lora.cpp), along with setWorkspace(). The stream parameter flows from loraOp.cpp through LoraImpl::run() to _runGemm() where setStream() is called appropriately. Adding setStream() in loraOp.cpp would be redundant and goes against the intended architectural design.

Applied to files:

  • cpp/tensorrt_llm/thop/loraOp.cpp
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PR_Github #15801 [ run ] completed with state SUCCESS
/LLM/release-1.0/L0_MergeRequest_PR pipeline #217 completed with status: 'SUCCESS'
Pipeline passed with automatic retried tests. Check the rerun report for details.

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amitz-nv merged commit 3efe1d9 into NVIDIA:release/1.0 Aug 20, 2025
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yuanjingx87 pushed a commit that referenced this pull request Aug 20, 2025
…ed_gemm every call (#7053)

Signed-off-by: Amit Zuker <203509407+amitz-nv@users.noreply.github.com>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 5, 2025
…ed_gemm every call (NVIDIA#7053)

Signed-off-by: Amit Zuker <203509407+amitz-nv@users.noreply.github.com>
Signed-off-by: Wangshanshan <30051912+dominicshanshan@users.noreply.github.com>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 5, 2025
…ed_gemm every call (NVIDIA#7053)

Signed-off-by: Amit Zuker <203509407+amitz-nv@users.noreply.github.com>
Signed-off-by: Wangshanshan <30051912+dominicshanshan@users.noreply.github.com>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 6, 2025
…ed_gemm every call (NVIDIA#7053)

Signed-off-by: Amit Zuker <203509407+amitz-nv@users.noreply.github.com>
Signed-off-by: Wangshanshan <30051912+dominicshanshan@users.noreply.github.com>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 6, 2025
…ed_gemm every call (NVIDIA#7053)

Signed-off-by: Amit Zuker <203509407+amitz-nv@users.noreply.github.com>
Signed-off-by: Wangshanshan <30051912+dominicshanshan@users.noreply.github.com>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Sep 7, 2025
…ed_gemm every call (NVIDIA#7053)

Signed-off-by: Amit Zuker <203509407+amitz-nv@users.noreply.github.com>
Signed-off-by: Wangshanshan <30051912+dominicshanshan@users.noreply.github.com>
chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request Apr 8, 2026
…ings

Clarify that GMS refers to GPU Memory Service from the Dynamo ecosystem.
Update terminology notes, challenge mitigations, and risk assessment to
reference the concrete prototype at ai-dynamo/dynamo#7053 including the
post_load_weights()/next_attn module-path-resolution fix, the validated
sleep/wake KV cache tag separation, and the local fallback path for
non-Ray executors.

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
Made-with: Cursor
chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request Apr 8, 2026
…odel and reduce timeline

Address review feedback:
- Clarify that MX/GMS are library dependencies, not reimplementations
- Separate TRT-LLM-side work from Dynamo-side work
- Reduce timeline from 18-22 weeks to 8-11 weeks
- Add glossary (GDS = GPUDirect Storage, etc.)
- Scope explicitly to PyTorch backend, V1 KV cache manager, C++ transceiver
- Reference PR NVIDIA#7053 prototype patterns for GMS integration

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
Made-with: Cursor
chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request Apr 10, 2026
…ings

Clarify that GMS refers to GPU Memory Service from the Dynamo ecosystem.
Update terminology notes, challenge mitigations, and risk assessment to
reference the concrete prototype at ai-dynamo/dynamo#7053 including the
post_load_weights()/next_attn module-path-resolution fix, the validated
sleep/wake KV cache tag separation, and the local fallback path for
non-Ray executors.

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
Made-with: Cursor
chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request Apr 10, 2026
…odel and reduce timeline

Address review feedback:
- Clarify that MX/GMS are library dependencies, not reimplementations
- Separate TRT-LLM-side work from Dynamo-side work
- Reduce timeline from 18-22 weeks to 8-11 weeks
- Add glossary (GDS = GPUDirect Storage, etc.)
- Scope explicitly to PyTorch backend, V1 KV cache manager, C++ transceiver
- Reference PR NVIDIA#7053 prototype patterns for GMS integration

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
Made-with: Cursor
chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request Apr 13, 2026
…ings

Clarify that GMS refers to GPU Memory Service from the Dynamo ecosystem.
Update terminology notes, challenge mitigations, and risk assessment to
reference the concrete prototype at ai-dynamo/dynamo#7053 including the
post_load_weights()/next_attn module-path-resolution fix, the validated
sleep/wake KV cache tag separation, and the local fallback path for
non-Ray executors.

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
Made-with: Cursor
chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request Apr 13, 2026
…odel and reduce timeline

Address review feedback:
- Clarify that MX/GMS are library dependencies, not reimplementations
- Separate TRT-LLM-side work from Dynamo-side work
- Reduce timeline from 18-22 weeks to 8-11 weeks
- Add glossary (GDS = GPUDirect Storage, etc.)
- Scope explicitly to PyTorch backend, V1 KV cache manager, C++ transceiver
- Reference PR NVIDIA#7053 prototype patterns for GMS integration

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
Made-with: Cursor
chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request May 20, 2026
…view

Apply 5 review-driven edits to §16 to address residual concerns:

Walk ordering (concern NVIDIA#8): change GMS RO and MX-receiver alias walks
from per-module to top-level model.setup_aliases(). Matches the §7
mitigation contract from ai-dynamo/dynamo PR NVIDIA#7053 ("Call
model.post_load_weights() (top-level only) before
materialize_module_from_gms()"). transform_weights() and
cache_derived_state() walks remain per-module since those bodies live
on submodules. New "Why setup_aliases() is top-level-only" callout
documents the asymmetry.

Lifecycle of _weights_transformed (concern #4): new subsection
specifying explicit set/reset/orthogonality rules. Includes a 2x2
truth table showing _weights_removed and _weights_transformed track
different lifecycles and can take any combination. Reset is the
orchestrator's responsibility (e.g., ModelLoader.reload() resets the
flag before re-binding tensors); subclasses do not manage reset.

Hard preconditions (concern #5): promote MX source-identity
completeness from "open question" to "hard precondition P1." Lists
transform-affecting parameters that MX identity must cover
(attn_backend, quant backend list, FP8/NVFP4 fusion strategy, TP/EP
layout, model revision). Specifies an in-tree backend-fingerprint
fail-safe as the fallback if upstream MX cannot guarantee
completeness. P2 documents that orchestrator owns _weights_transformed
reset. Removes redundant open question NVIDIA#6 from the table.

Cosmetic fixes (concerns #2, NVIDIA#6): "four stages" -> "three per-module
stages plus orchestrator-managed per-process finalization."
cache_derived_state description softened to "reserved for
data-dependent state where it exists; many existing modules will have
empty bodies."

Scope clarifications (concerns #1, #3, NVIDIA#7):
- Tiny PR scope reframed as "duck-typed helpers, not inheritance"
  with citations to existing model_loader.py walker pattern. Lists
  4 walker helpers (_setup_aliases, _walk_transform, _walk_cache_state,
  _walk_full_post_load).
- Migration callout: when migrating a subclass, the old
  post_load_weights() override MUST be removed; otherwise the new
  staged calls silently no-op.
- Family PR #2 (Linear/Attention) gains a "quant-method callback
  decision" note with default = keep quant_method.post_load_weights
  callback name (no rename).

No code changes. Drives Tiny prep PR scope and family-PR migration
sequence. References:
- TRT-LLM PR NVIDIA#13926 (GMS-only)
- TRT-LLM PR NVIDIA#14151 (MX shim refactor)
- ai-dynamo/dynamo PR NVIDIA#7053 (upstream GMS prototype)

Signed-off-by: Chien-Chun Hung <chienchunh@nvidia.com>
Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request May 31, 2026
Updates the in-tree staged-hook design doc now that the prep PR has
landed:

- Status flipped from "Draft" to "Locked (2026-05-30)"; Wave 1 (alias
  migration + GMS-RO cutover) is named as the immediate next step.
- Restructure the Implementation plan into a Phase-status table plus
  four named Waves with explicit scope, blast radius, risk class, LOC
  estimate, MX receiver value, and gate criteria per wave.
- Add Wave 4 (MX publish-after-transform flip + P1 fail-safe + receiver
  cutover) covering the publisher flip dependency on Waves 2-3, the
  in-tree fingerprint check that answers the homogeneity-assumption
  hazard, and a per-model allow-list for incremental rollout.
- Add a Per-model incremental rollout section explaining how Waves 2/3
  stage models into the Wave-4 allow-list one at a time.
- Cite contributing PRs by JIRA ticket / descriptive title only, to
  avoid creating cross-references on the underlying NVIDIA/TensorRT-LLM
  PRs from this private docs-and-plans branch. ai-dynamo/dynamo PR
  NVIDIA#7053 is retained verbatim since it lives in a different repo/org.

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
chienchunhung added a commit to chienchunhung/TensorRT-LLM that referenced this pull request Jun 1, 2026
Sync the in-tree design doc with the standalone version kept offline
(2026-05-31 last update). Substantive additions / corrections:

- Foundation references section: split into merged (TRTLLM-11851, -12440,
  end-to-end prototype) and inflight (TRTLLM-13077 prep PR, MX-team
  Delegate-to-ModelExpress refactor proposal) sub-sections.
- Audience and intent section: name the two intended readers (MX/GMS
  upstream engineers + TRT-LLM code owners) and what each needs to take
  away.
- P1 precondition reframed: source-identity matching is fundamentally a
  TRT-LLM concern (only TRT-LLM knows which knobs affect layout), so the
  API surface lives in TRT-LLM as `tllm.disagg.compute_source_identity()`
  / `is_source_compatible()` and is consumed by both MX and GMS.  The
  opaque-bytes design protects transport libraries from churn when
  TRT-LLM adds new layout-affecting parameters.
- Wave 4 scope updated to land the TRT-LLM source-identity API (~80 LOC)
  as a foundational sub-step, used by both MX and GMS receiver paths.
- New "Coordination with MX and GMS" section:
  - Source-identity API directionality (TRT-LLM-owned, MX/GMS-consumed).
  - Scope of MX checkpoint loading: discusses the wholesale vs.
    transport-only delegation question raised by the MX-team refactor
    proposal, with TRT-LLM advocating transport-only (fallback /
    validation / telemetry concerns are TRT-LLM-internal and parallel
    the NIXL/UCX division-of-labor model in the disagg KV-cache
    transceiver).
  - What this asks of MX vs. what this asks of GMS as separate bullets.
- Status / Created / Last-updated header brought to 2026-05-31.

All PR-number cross-references (NVIDIA#13531, NVIDIA#13926, NVIDIA#13045, NVIDIA#14770, NVIDIA#14151)
deliberately omitted to keep this docs-and-plans branch from triggering
back-references on the public NVIDIA/TensorRT-LLM PRs; cited via JIRA
tickets and descriptive titles instead.  Only external cross-ref
retained is ai-dynamo/dynamo PR NVIDIA#7053 (different repo/org).

Signed-off-by: Chien-Chun Hung <2679986+chienchunhung@users.noreply.github.com>
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3 participants