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Add Unix socket transport for QEMU testing#9

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widgetii merged 1 commit intomasterfrom
socket-transport
Mar 30, 2026
Merged

Add Unix socket transport for QEMU testing#9
widgetii merged 1 commit intomasterfrom
socket-transport

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Summary

  • Adds SocketTransport class (src/defib/transport/socket.py) for connecting to QEMU chardev Unix sockets
  • Updates create_transport() to detect socket:// prefix and route to the new transport
  • Documents QEMU testing workflow in README

Usage

# Start qemu-hisilicon in fastboot mode (no -kernel)
qemu-system-arm -M hi3516ev300 -m 64M -nographic \
    -chardev socket,id=ser0,path=/tmp/qemu.sock,server=on,wait=off \
    -serial chardev:ser0

# Load firmware via defib
defib burn -c hi3516ev300 -p socket:///tmp/qemu.sock

Test plan

  • Protocol test: DDR (64B) + SPL (24KB) + U-Boot (236KB) transfer against QEMU hisi-fastboot device
  • Full transfer completes in ~160ms with CRC-16 validation on every frame
  • Existing serial transport unaffected (socket:// prefix opt-in only)
  • CI: defib unit tests still pass

🤖 Generated with Claude Code

Adds a SocketTransport class that connects to QEMU's chardev Unix
sockets, enabling end-to-end protocol testing without physical hardware.
The transport factory now accepts a `socket://` prefix on the port
argument (e.g. `defib burn -c hi3516ev300 -p socket:///tmp/qemu.sock`).

flush_input() is a no-op for sockets since, unlike serial ports, there
is no stale data to drain — flushing would discard legitimate ACK
responses that QEMU has already sent back.

Tested against qemu-hisilicon's hisi-fastboot device: full 3-stage
transfer (DDR + SPL + 236 KB U-Boot) completes in ~160 ms with CRC
validation on every frame.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
widgetii pushed a commit to widgetii/qemu-hisilicon that referenced this pull request Mar 30, 2026
Emulates the HiSilicon boot ROM UART download protocol (Protocol 1 -
Standard). When QEMU starts without -kernel, the hisi-fastboot device
takes over UART0, sends 0x20 handshake bytes, and accepts firmware
uploads via HEAD/DATA/TAIL frames with CRC-16/CCITT validation.

After all three transfers (DDR init, SPL, U-Boot) complete, the chardev
is handed off to a newly-created PL011 and the CPU starts at the U-Boot
entry point. The existing -kernel boot path is unchanged.

Tested end-to-end with defib (OpenIPC/defib#9): 236 KB OpenIPC U-Boot
transferred in ~160 ms over Unix socket.

New files:
  qemu/hw/misc/hisi-fastboot.c      - boot ROM protocol device
  qemu/include/hw/misc/hisi-fastboot.h - public header
  qemu-boot/test-fastboot-protocol.py  - protocol-level test
  qemu-boot/test-fastboot.sh           - end-to-end test with defib

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
@widgetii widgetii merged commit ee9bd1c into master Mar 30, 2026
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