asap7: constraints.sdc max delay excludes clock latency

[oharboe]

#3337 (comment)

Metric	Old	New	Type
synth__design__instance__area__stdcell	35273.33	34554.19	Tighten
finish__timing__setup__ws	-457.76	-89.95	Tighten
finish__timing__drv__setup_violation_count	605	536	Tighten
finish__timing__wns_percent_delay	-111.1	-31.9	Tighten

[oharboe]

@tspyrou @maliberty -ignore_clock_latency appears not to account for clock insertion latency within macros.

Is that correct?

Can or should OpenSTA account for clock latency in macros?

The only thing I can think of is extend the ORFS flow to include a .v alongside the .lib file for abstracts to have the option for more detailed/accurate, and slower, OpenSTA timing reports.

Here, 145.89 would be 65.89 ignoring clock latency inside the macro:

   0.00    0.00 ^ ces_4_0/clock (Element)
 145.89  145.89 v ces_4_0/io_outs_left[7] (Element)

From within Element macro:

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00 ^ io_outs_left_REG[7]$_DFF_P_/CLK (DFFHQNx1_ASAP7_75t_R)
  44.92   44.92 ^ io_outs_left_REG[7]$_DFF_P_/QN (DFFHQNx1_ASAP7_75t_R)
   8.65   53.57 v _1378_/Y (INVx1_ASAP7_75t_R)
  12.32   65.88 v output103/Y (BUFx3_ASAP7_75t_R)
   0.00   65.89 v io_outs_left[7] (out)
          65.89   data arrival time

from mock-array:

>>> report_checks -path_group reg2out 
Startpoint: ces_4_0 (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_outs_left_4[7] (output port)
Path Group: reg2out
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00 ^ ces_4_0/clock (Element)
 145.89  145.89 v ces_4_0/io_outs_left[7] (Element)
  11.54  157.42 v output2942/Y (BUFx3_ASAP7_75t_R)
   0.03  157.45 v io_outs_left_4[7] (out)
         157.45   data arrival time

  80.00   80.00   max_delay
   0.00   80.00   output external delay
          80.00   data required time
---------------------------------------------------------
          80.00   data required time
        -157.45   data arrival time
---------------------------------------------------------
         -77.45   slack (VIOLATED)

Path within the Element:

>>> report_checks -to {io_outs_left[7]}
Startpoint: io_outs_left_REG[7]$_DFF_P_
            (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_outs_left[7] (output port)
Path Group: reg2out
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00 ^ io_outs_left_REG[7]$_DFF_P_/CLK (DFFHQNx1_ASAP7_75t_R)
  44.92   44.92 ^ io_outs_left_REG[7]$_DFF_P_/QN (DFFHQNx1_ASAP7_75t_R)
   8.65   53.57 v _1378_/Y (INVx1_ASAP7_75t_R)
  12.32   65.88 v output103/Y (BUFx3_ASAP7_75t_R)
   0.00   65.89 v io_outs_left[7] (out)
          65.89   data arrival time

  80.00   80.00   max_delay
   0.00   80.00   output external delay
          80.00   data required time
---------------------------------------------------------
          80.00   data required time
         -65.89   data arrival time
---------------------------------------------------------
          14.11   slack (MET)


>>> report_checks -to {io_outs_left_REG[7]$_DFF_P_}
Startpoint: io_outs_left_mult.o[7]$_DFF_P_
            (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_outs_left_REG[7]$_DFF_P_
          (rising edge-triggered flip-flop clocked by clock)
Path Group: reg2reg
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
  77.51   77.51   clock network delay (propagated)
   0.00   77.51 ^ io_outs_left_mult.o[7]$_DFF_P_/CLK (DFFHQNx1_ASAP7_75t_R)
  39.74  117.25 v io_outs_left_mult.o[7]$_DFF_P_/QN (DFFHQNx1_ASAP7_75t_R)
   7.40  124.65 ^ _0740_/Y (INVx1_ASAP7_75t_R)
   0.07  124.72 ^ io_outs_left_REG[7]$_DFF_P_/D (DFFHQNx1_ASAP7_75t_R)
         124.72   data arrival time

 250.00  250.00   clock clock (rise edge)
  72.07  322.07   clock network delay (propagated)
   4.61  326.68   clock reconvergence pessimism
         326.68 ^ io_outs_left_REG[7]$_DFF_P_/CLK (DFFHQNx1_ASAP7_75t_R)
  -5.01  321.67   library setup time
         321.67   data required time
---------------------------------------------------------
         321.67   data required time
        -124.72   data arrival time
---------------------------------------------------------
         196.95   slack (MET)

[maliberty]

I'll leave it to @tspyrou to comment on what is considered correct.

[oharboe]

I'll leave it to @tspyrou to comment on what is considered correct.

the reg2out, in2out and in2reg max delay paths are there only as an overconstrainted optimization target.

Of course we'll wait for @tspyrou, but I think this PR is good to merge as we're expressing the correct intent in the constraints.sdc file now.

Timing closure as per platforms/asap7/constraints.sdc is only intended to be verified for reg2reg paths. For mock-array, reg2out, in2out and in2reg paths will be part of reg2reg paths where the mock-array is used.