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Test retiming#3399

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maliberty merged 1 commit into
The-OpenROAD-Project:masterfrom
The-OpenROAD-Project-staging:synth-retime
Aug 15, 2025
Merged

Test retiming#3399
maliberty merged 1 commit into
The-OpenROAD-Project:masterfrom
The-OpenROAD-Project-staging:synth-retime

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Test abc retiming on Oyvind's design from #3337

See the post-cts critical reg2reg path without the retiming step:


Startpoint: a_pipe[3][6]$_DFF_P_
            (rising edge-triggered flip-flop clocked by clock)
Endpoint: mul_result[31]$_DFF_P_
          (rising edge-triggered flip-flop clocked by clock)
Path Group: reg2reg
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
 100.46  100.46   clock network delay (propagated)
   0.00  100.46 ^ a_pipe[3][6]$_DFF_P_/CLK (DFFHQNx3_ASAP7_75t_R)
  52.47  152.93 v a_pipe[3][6]$_DFF_P_/QN (DFFHQNx3_ASAP7_75t_R)
  20.58  173.51 v place1153/Y (BUFx6f_ASAP7_75t_R)
  15.65  189.16 v place1154/Y (BUFx12f_ASAP7_75t_R)
   8.53  197.68 ^ _2434_/Y (NOR2x2_ASAP7_75t_R)
  55.42  253.11 v _3148_/SN (FAx1_ASAP7_75t_R)
  47.89  301.00 v _3149_/SN (FAx1_ASAP7_75t_R)
  15.75  316.75 ^ _2969_/Y (INVx1_ASAP7_75t_R)
  21.74  338.49 v _3150_/CON (FAx1_ASAP7_75t_R)
  17.40  355.89 ^ _3150_/SN (FAx1_ASAP7_75t_R)
  15.87  371.76 v _2974_/Y (INVx1_ASAP7_75t_R)
  32.21  403.97 ^ _3154_/CON (FAx1_ASAP7_75t_R)
  17.75  421.73 v _3154_/SN (FAx1_ASAP7_75t_R)
  15.79  437.52 ^ _2982_/Y (INVx1_ASAP7_75t_R)
  39.77  477.29 ^ _3155_/SN (FAx1_ASAP7_75t_R)
  18.09  495.38 v _3301_/CON (HAxp5_ASAP7_75t_R)
  12.71  508.09 ^ _3301_/SN (HAxp5_ASAP7_75t_R)
   9.64  517.73 v _2435_/Y (INVx1_ASAP7_75t_R)
  37.09  554.82 v _3302_/SN (HAxp5_ASAP7_75t_R)
  21.76  576.59 v _1921_/Y (OA21x2_ASAP7_75t_R)
  21.21  597.79 v _1922_/Y (OA211x2_ASAP7_75t_R)
  21.53  619.32 v _1923_/Y (OA31x2_ASAP7_75t_R)
  28.23  647.55 v _1960_/Y (OA211x2_ASAP7_75t_R)
  21.64  669.19 v _2028_/Y (OA31x2_ASAP7_75t_R)
  26.37  695.57 v _2051_/Y (OA211x2_ASAP7_75t_R)
  17.65  713.21 v _2052_/Y (OA21x2_ASAP7_75t_R)
  26.60  739.81 ^ _2053_/Y (XOR2x2_ASAP7_75t_R)
   0.01  739.82 ^ mul_result[31]$_DFF_P_/D (DFFHQNx3_ASAP7_75t_R)
         739.82   data arrival time

 250.00  250.00   clock clock (rise edge)
  89.85  339.85   clock network delay (propagated)
   3.47  343.32   clock reconvergence pessimism
         343.32 ^ mul_result[31]$_DFF_P_/CLK (DFFHQNx3_ASAP7_75t_R)
  -5.81  337.51   library setup time
         337.51   data required time
---------------------------------------------------------
         337.51   data required time
        -739.82   data arrival time
---------------------------------------------------------
        -402.31   slack (VIOLATED)

vs with the retiming step:

Startpoint: _3887_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: _3879_ (rising edge-triggered flip-flop clocked by clock)
Path Group: reg2reg
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
 133.56  133.56   clock network delay (propagated)
   0.00  133.56 ^ _3887_/CLK (DFFHQNx3_ASAP7_75t_R)
  50.06  183.62 ^ _3887_/QN (DFFHQNx3_ASAP7_75t_R)
  15.35  198.97 v _4600_/CON (HAxp5_ASAP7_75t_R)
  17.22  216.19 ^ _3445_/Y (NAND2x1_ASAP7_75t_R)
  32.29  248.48 v _3446_/Y (XNOR2x2_ASAP7_75t_R)
  13.70  262.18 v rebuffer15/Y (BUFx3_ASAP7_75t_R)
  25.34  287.51 v _4602_/SN (HAxp5_ASAP7_75t_R)
  18.36  305.87 v place594/Y (BUFx3_ASAP7_75t_R)
  29.87  335.75 v _3337_/Y (OR4x1_ASAP7_75t_R)
  22.38  358.13 v _3339_/Y (OR2x2_ASAP7_75t_R)
  26.63  384.76 v _3579_/Y (OR4x1_ASAP7_75t_R)
  28.16  412.91 v _3580_/Y (OA211x2_ASAP7_75t_R)
  20.73  433.64 v _3583_/Y (AO221x1_ASAP7_75t_R)
   0.01  433.65 v _3879_/D (DFFHQNx3_ASAP7_75t_R)
         433.65   data arrival time

 250.00  250.00   clock clock (rise edge)
 125.07  375.07   clock network delay (propagated)
   3.42  378.49   clock reconvergence pessimism
         378.49 ^ _3879_/CLK (DFFHQNx3_ASAP7_75t_R)
   1.90  380.39   library setup time
         380.39   data required time
---------------------------------------------------------
         380.39   data required time
        -433.65   data arrival time
---------------------------------------------------------
         -53.26   slack (VIOLATED)

@oharboe
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oharboe commented Aug 14, 2025

😌

Signed-off-by: Martin Povišer <povik@cutebit.org>
@povik
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povik commented Aug 15, 2025

@maliberty It should be good to merge now

@maliberty maliberty merged commit bb23980 into The-OpenROAD-Project:master Aug 15, 2025
7 of 8 checks passed
@maliberty maliberty deleted the synth-retime branch August 15, 2025 17:17
Comment thread flow/scripts/synth.tcl
memory_map
opt -full
techmap
abc -dff -script scripts/abc_retime.script
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@povik @maliberty The path fix is gone...

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Oops, let me fix

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4 participants