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jpeg_rle: Add missing reset to ddstrb pipeline register to prevent spurious go after reset #4118

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Merged
maliberty merged 2 commits into from
Apr 14, 2026
Merged

jpeg_rle: Add missing reset to ddstrb pipeline register to prevent spurious go after reset #4118

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ee431af
rtl: fix missing reset on ddstrb in jpeg_rle
ashnaaseth2325-oss Apr 7, 2026
6937b58
Update metrics for sky130hd/hs jpeg
maliberty Apr 14, 2026
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12 changes: 6 additions & 6 deletions flow/designs/sky130hd/jpeg/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -155.0,
"value": -170.0,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand All @@ -44,15 +44,15 @@
"compare": ">="
},
"globalroute__antenna_diodes_count": {
"value": 100,
"value": 115,
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -0.899,
"value": -1.16,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -201.0,
"value": -268.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand Down Expand Up @@ -80,11 +80,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -0.603,
"value": -0.943,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -96.0,
"value": -146.0,
"compare": ">="
},
"finish__timing__hold__ws": {
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10 changes: 5 additions & 5 deletions flow/designs/sky130hs/jpeg/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -12,19 +12,19 @@
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 56019,
"value": 55868,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 4871,
"value": 4858,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 4871,
"value": 4858,
"compare": "<="
},
"cts__timing__setup__ws": {
Expand Down Expand Up @@ -52,7 +52,7 @@
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -0.809,
"value": -1.92,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand All @@ -76,7 +76,7 @@
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
"value": 100,
"value": 102,
"compare": "<="
},
"finish__timing__setup__ws": {
Expand Down
7 changes: 5 additions & 2 deletions flow/designs/src/jpeg/jpeg_rle.v
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Expand Up @@ -98,8 +98,11 @@ module jpeg_rle(clk, rst, ena, dstrb, din, size, rlen, amp, douten, bstart);
//

reg ddstrb;
always @(posedge clk)
ddstrb <= #1 dstrb;
always @(posedge clk or negedge rst)
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if (!rst)
ddstrb <= #1 1'b0;
else
ddstrb <= #1 dstrb;

// generate run-length encoded signals
jpeg_rle1 rle(
Expand Down