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asap7: drop fictitious set_input/output_delay from single-clock macro SDCs #4170

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Merged
maliberty merged 5 commits into from
Apr 23, 2026
Merged

asap7: drop fictitious set_input/output_delay from single-clock macro SDCs #4170

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0dfc20b
asap7: drop fictitious set_input/output_delay from single-clock macro…
oharboe Apr 21, 2026
0aba8ee
asap7: refresh rules-base.json for aes-block and aes-mbff
oharboe Apr 22, 2026
29dc481
asap7: regenerate rules-base.json via make update_ok
oharboe Apr 22, 2026
c1d9d1f
Merge remote-tracking branch 'origin/master' into HEAD
oharboe Apr 23, 2026
cd586bc
asap7: refresh rules-base.json for mock-alu
oharboe Apr 23, 2026
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15 changes: 7 additions & 8 deletions flow/designs/asap7/aes-block/constraint.sdc
View file
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Original file line number Diff line number Diff line change
@@ -1,13 +1,12 @@
set clk_name clk
set clk_port_name clk
set clk_period 450
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
# Match the old set_input/output_delay = 0.2 * clk_period budget, as
# optimization targets only (no set_input/output_delay — see rationale in
# $PLATFORM_DIR/constraints.sdc).
set in2reg_max [expr { $clk_period * 0.8 }]
set reg2out_max [expr { $clk_period * 0.8 }]
set in2out_max [expr { $clk_period * 0.6 }]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [all_inputs -no_clocks]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
source $::env(PLATFORM_DIR)/constraints.sdc
20 changes: 10 additions & 10 deletions flow/designs/asap7/aes-block/rules-base.json
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Original file line number Diff line number Diff line change
Expand Up @@ -28,19 +28,19 @@
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -78.0,
"value": -113.0,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -4840.0,
"value": -7390.0,
"compare": ">="
},
"cts__timing__hold__ws": {
"value": -52.3,
"value": -22.5,
"compare": ">="
},
"cts__timing__hold__tns": {
"value": -6310.0,
"value": -90.0,
"compare": ">="
},
"globalroute__antenna_diodes_count": {
Expand All @@ -52,19 +52,19 @@
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -3660.0,
"value": -6000.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
"value": -25.9,
"value": -22.5,
"compare": ">="
},
"globalroute__timing__hold__tns": {
"value": -1080.0,
"value": -90.0,
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 51873,
"value": 49870,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -80,11 +80,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -94.0,
"value": -91.5,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -1470.0,
"value": -2720.0,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand Down
15 changes: 7 additions & 8 deletions flow/designs/asap7/aes-mbff/constraint.sdc
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,13 +1,12 @@
set clk_name clk
set clk_port_name clk
set clk_period 380
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
# Match the old set_input/output_delay = 0.2 * clk_period budget, as
# optimization targets only (no set_input/output_delay — see rationale in
# $PLATFORM_DIR/constraints.sdc).
set in2reg_max [expr { $clk_period * 0.8 }]
set reg2out_max [expr { $clk_period * 0.8 }]
set in2out_max [expr { $clk_period * 0.6 }]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [all_inputs -no_clocks]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
source $::env(PLATFORM_DIR)/constraints.sdc
14 changes: 7 additions & 7 deletions flow/designs/asap7/aes-mbff/rules-base.json
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 2103,
"value": 2087,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
Expand All @@ -28,11 +28,11 @@
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -28.8,
"value": -26.6,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -164.0,
"value": -146.0,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand All @@ -48,11 +48,11 @@
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -41.3,
"value": -37.1,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -1010.0,
"value": -622.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand Down Expand Up @@ -84,7 +84,7 @@
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -235.0,
"value": -185.0,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand All @@ -96,7 +96,7 @@
"compare": ">="
},
"finish__design__instance__area": {
"value": 2206,
"value": 2180,
"compare": "<="
}
}
15 changes: 7 additions & 8 deletions flow/designs/asap7/aes_lvt/constraint.sdc
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,13 +1,12 @@
set clk_name clk
set clk_port_name clk
set clk_period 360
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
# Match the old set_input/output_delay = 0.2 * clk_period budget, as
# optimization targets only (no set_input/output_delay — see rationale in
# $PLATFORM_DIR/constraints.sdc).
set in2reg_max [expr { $clk_period * 0.8 }]
set reg2out_max [expr { $clk_period * 0.8 }]
set in2out_max [expr { $clk_period * 0.6 }]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [all_inputs -no_clocks]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
source $::env(PLATFORM_DIR)/constraints.sdc
18 changes: 9 additions & 9 deletions flow/designs/asap7/aes_lvt/rules-base.json
View file
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Original file line number Diff line number Diff line change
@@ -1,30 +1,30 @@
{
"synth__design__instance__area__stdcell": {
"value": 1910.0,
"value": 1780.0,
"compare": "<="
},
"constraints__clocks__count": {
"value": 1,
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 1954,
"value": 1818,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 17740,
"value": 17450,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 1543,
"value": 1517,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 1543,
"value": 1517,
"compare": "<="
},
"cts__timing__setup__ws": {
Expand Down Expand Up @@ -64,7 +64,7 @@
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 68956,
"value": 65052,
"compare": "<="
},
"detailedroute__route__drc_errors": {
Expand All @@ -80,11 +80,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -18.0,
"value": -46.8,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -72.0,
"value": -219.0,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand All @@ -96,7 +96,7 @@
"compare": ">="
},
"finish__design__instance__area": {
"value": 1992,
"value": 1846,
"compare": "<="
}
}
15 changes: 7 additions & 8 deletions flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -3,15 +3,14 @@ current_design jpeg_encoder
set clk_name clk
set clk_port_name clk
set clk_period 680
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
# Match the old set_input/output_delay = 0.2 * clk_period budget, as
# optimization targets only (no set_input/output_delay — see rationale in
# $PLATFORM_DIR/constraints.sdc).
set in2reg_max [expr { $clk_period * 0.8 }]
set reg2out_max [expr { $clk_period * 0.8 }]
set in2out_max [expr { $clk_period * 0.6 }]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [all_inputs -no_clocks]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
source $::env(PLATFORM_DIR)/constraints.sdc

set_max_fanout 10 [current_design]
15 changes: 7 additions & 8 deletions flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -3,13 +3,12 @@ current_design jpeg_encoder
set clk_name clk
set clk_port_name clk
set clk_period 600
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
# Match the old set_input/output_delay = 0.2 * clk_period budget, as
# optimization targets only (no set_input/output_delay — see rationale in
# $PLATFORM_DIR/constraints.sdc).
set in2reg_max [expr { $clk_period * 0.8 }]
set reg2out_max [expr { $clk_period * 0.8 }]
set in2out_max [expr { $clk_period * 0.6 }]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [all_inputs -no_clocks]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
source $::env(PLATFORM_DIR)/constraints.sdc
16 changes: 8 additions & 8 deletions flow/designs/asap7/mock-alu/constraints.sdc
View file
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Original file line number Diff line number Diff line change
@@ -1,16 +1,16 @@
set clk_name clock
set clk_port_name clock
set clk_period 300
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
# Match the old set_input_delay = 0.7 * clk_period (tight, stress-test)
# and set_output_delay = 0.2 * clk_period budgets, as optimization targets
# only (no set_input/output_delay — see rationale in
# $PLATFORM_DIR/constraints.sdc).
set in2reg_max [expr { $clk_period * 0.3 }]
set reg2out_max [expr { $clk_period * 0.8 }]
set in2out_max [expr { $clk_period * 0.1 }]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [all_inputs -no_clocks]

set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
source $::env(PLATFORM_DIR)/constraints.sdc

set output_regs [get_cells *io_out_REG*]
if { [llength $output_regs] == 0 } {
Expand Down
12 changes: 6 additions & 6 deletions flow/designs/asap7/mock-alu/rules-base.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -28,11 +28,11 @@
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -308.0,
"value": -289.0,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -14100.0,
"value": -18200.0,
"compare": ">="
},
"cts__timing__hold__ws": {
Expand All @@ -48,11 +48,11 @@
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -321.0,
"value": -309.0,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -18100.0,
"value": -20700.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
Expand Down Expand Up @@ -80,11 +80,11 @@
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -303.0,
"value": -292.0,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -15700.0,
"value": -18500.0,
"compare": ">="
},
"finish__timing__hold__ws": {
Expand Down
15 changes: 7 additions & 8 deletions flow/designs/asap7/swerv_wrapper/constraint.sdc
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Original file line number Diff line number Diff line change
Expand Up @@ -3,13 +3,12 @@ current_design swerv_wrapper
set clk_name core_clock
set clk_port_name clk
set clk_period 1600
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]
# Match the old set_input/output_delay = 0.2 * clk_period budget, as
# optimization targets only (no set_input/output_delay — see rationale in
# $PLATFORM_DIR/constraints.sdc).
set in2reg_max [expr { $clk_period * 0.8 }]
set reg2out_max [expr { $clk_period * 0.8 }]
set in2out_max [expr { $clk_period * 0.6 }]

create_clock -name $clk_name -period $clk_period $clk_port

set non_clock_inputs [all_inputs -no_clocks]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
source $::env(PLATFORM_DIR)/constraints.sdc
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