Clock Mesh Extension of CTS/PDN

[QuantamHD]

@arlpetergadfort Came across this slide deck on the creation of Clock Meshes. Seems like it makes CTS much easier at the cost of higher power.

Do you think you and I could extend PDN to generate the clock mesh, and then we could hook up the CTS to this new clock distribution network?

[maliberty]

It also takes up more routing resource but is a valid strategy for some cases. There is a bunch of ongoing enhancement to the current CTS but I'm open to having further contributions so long as we coordinate to avoid collisions. We are far from optimal in our current approach and I think a lot of benefit will be realized with the current work.

[mithro]

@QuantamHD - @mkkassem used a clock mesh on the metal layer to fix the hold issues on the ChipIgnite-1 silicon.

[mithro]

@mguthaus from OpenRAM also had a poster on clock meshes on his wall when I last visited.

[maliberty]

@QuantamHD - @mkkassem used a clock mesh on the metal layer to fix the hold issues on the ChipIgnite-1 silicon.

I believe it was more of adding ad-hoc crosslinks in the clock tree rather than a true mesh.

[maliberty]

Note that delay calculation for meshes is much harder due to the multiple drivers and is not currently supported in sta. With CCS it would become possible.

[mithro]

@maliberty - I believe @mkkassem just did spice simulation of the clocks for STA analysis?

[maliberty]

@mithro yes but you need to build a flow to back annotate those results into sta so you can do optimization/signoff. That is the pre-CCS methodology. If we want to make this generally available someone will need to automate that.

[QuantamHD]

I assumed we could link in ngspice to do that for us.

[mithro]

@maliberty - Is there a potential way to create a generic way to send things to a spice simulator and pull the timing information back into OpenROAD (even if extremely slow)?

[mithro]

Is there some relationship with BigSpicy? https://github.com/google/bigspicy

[gadfort]

@QuantamHD I see why you would want to use PDN for this, but I think it would be better to augment CTS to be able to build the grid itself and we can work to expose the DRC checking in PDN to be able to build vias and the grid correctly?

[maliberty]

Perhaps there is some code that could be an odb utility which both could share

[tspyrou]

@mithro I think that for a flow like this to work there would have to be a layer on top of the circuit simulator which sets up stage based runs. If the mesh is levelized from inputs to register leafs, each level can be run in parallel and in order with level 2 using slew waveforms from level one etc. From there an SDF can be generated which is fed into STA. This is a well known approach to clock mesh spice simulation which is scalable and accurate. These numbers can also be used as a baseline to measure STA accuracy when STA is enhanced to support meshes.