write_timing_model doesn't consider set_timing_derate

[precisionmoon]

Describe the bug

write_timing_model uses original timing from libraries without considering impact from set_timing_derate.

Expected Behavior

It'd be good if write_timing_model and report_checks have the same behavior related to set_timing_derate.

Environment

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kernel: Linux 5.19.0-1027-gcp
os: Ubuntu 22.04.2 LTS (Jammy Jellyfish)
cmake version 3.24.2
-- The CXX compiler identification is GNU 11.4.0
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-- OpenROAD version: v2.0-11396-g137ea7c81
-- System name: Linux
-- Compiler: GNU 11.4.0
-- Build type: RELEASE
-- Install prefix: /usr/local
-- C++ Standard: 17
-- C++ Standard Required: ON
-- C++ Extensions: OFF
-- The C compiler identification is GNU 11.4.0
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-- Found Python: /usr/bin/python3.10 (found version "3.10.12") found components: Interpreter 
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-- Using SWIG >= 4.1.0 -flatstaticmethod flag for python
-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0")  
-- boost: 1.80.0
-- Found Python3: /usr/include/python3.10 (found version "3.10.12") found components: Development Development.Module Development.Embed 
-- Found ZLIB: /usr/lib/x86_64-linux-gnu/libz.so (found version "1.2.11") 
-- spdlog: 1.8.1
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-- Could NOT find Doxygen (missing: DOXYGEN_EXECUTABLE) 
-- STA version: 2.4.0
-- STA git sha: 60a45c13b7cfd9bd3919939a73290b7e6bf081e8
-- System name: Linux
-- Compiler: GNU 11.4.0
-- Build type: RELEASE
-- Build CXX_FLAGS: -O3 -DNDEBUG
-- Install prefix: /usr/local
-- Found FLEX: /usr/bin/flex (found version "2.6.4") 
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- SSTA: 0
-- STA executable: /home/cmoon/OR/cts_google/src/sta/app/sta
-- Found re2: /opt/or-tools/lib/cmake/re2/re2Config.cmake (found version "9.0.0") 
-- Found Clp: /opt/or-tools/lib/cmake/Clp/ClpConfig.cmake (found version "1.17.7") 
-- Found Cbc: /opt/or-tools/lib/cmake/Cbc/CbcConfig.cmake (found version "2.10.7") 
-- Found SCIP: /opt/or-tools/lib/cmake/scip/scip-config.cmake (found version "8.0.1") 
-- Found OpenMP_CXX: -fopenmp (found version "4.5") 
-- Found OpenMP: TRUE (found version "4.5")  
-- GPU is not enabled
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- Found Eigen3: /usr/local/share/eigen3/cmake/Eigen3Config.cmake (found version "3.4.0") 
-- GUI is enabled
-- Charts widget is not enabled
-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0") found components: serialization 
-- Could NOT find VTune (missing: VTune_LIBRARIES VTune_INCLUDE_DIRS) 
-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found suitable version "1.80.0", minimum required is "1.78")  
-- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
-- TCL header: /usr/include/tcl/tcl.h
-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version "1.80.0") found components: serialization system thread 
-- TCL readline enabled
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-- Python3 enabled
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-- Build files have been written to: /tmp/tmp.MdWNYl7qIL

To Reproduce

Instantiate a base cell and generate multiple

versions using set_timing_derate

set liberty_file "Nangate45/Nangate45_typ.lib"
read_lib $liberty_file
read_lib array_tile.lib

LEF is needed to create block

set tech_lef "Nangate45/Nangate45_tech.lef"
read_lef $tech_lef
set std_cell_lef "Nangate45/Nangate45_stdcell.lef"
read_lef $std_cell_lef
read_lef array_tile.lef

create block

set db [ord::get_db]
set chip [odb::dbChip_create $db]
set block [odb::dbBlock_create $chip "top"]

create IO nets

set clk_net [odb::dbNet_create $block "clk"]
set e_in_net [odb::dbNet_create $block "e_in"]
set w_in_net [odb::dbNet_create $block "w_in"]
set e_out_net [odb::dbNet_create $block "e_out"]
set w_out_net [odb::dbNet_create $block "w_out"]

create IO terminals

set clk_bterm [odb::dbBTerm_create $clk_net "clk"]
$clk_bterm setSigType CLOCK
$clk_bterm setIoType INPUT

set e_in_bterm [odb::dbBTerm_create $e_in_net "e_in"]
$e_in_bterm setSigType SIGNAL
$e_in_bterm setIoType INPUT

set w_in_bterm [odb::dbBTerm_create $e_in_net "w_in"]
$w_in_bterm setSigType SIGNAL
$w_in_bterm setIoType INPUT

set e_out_bterm [odb::dbBTerm_create $e_out_net "e_out"]
$e_out_bterm setSigType SIGNAL
$e_out_bterm setIoType OUTPUT

set w_out_bterm [odb::dbBTerm_create $w_out_net "w_out"]
$w_out_bterm setSigType SIGNAL
$w_out_bterm setIoType OUTPUT

create instance and connect to IO terminals

set master [$db findMaster "array_tile"]
set inst [odb::dbInst_create $block $master "inst_1"]
[$inst findITerm "clk"] connect $clk_net
[$inst findITerm "e_in"] connect $e_in_net
[$inst findITerm "w_in"] connect $w_in_net
[$inst findITerm "e_out"] connect $e_out_net
[$inst findITerm "w_out"] connect $w_out_net

create and link design

ord::design_created

create SDC

create_clock -period 5 clk
set_input_delay 0.0 {e_in w_in} -clock clk
set_output_delay 0.0 {e_out w_out} -clock clk

puts "#### baseline ####"
report_checks
write_timing_model -library_name base_lib -cell base base.lib

set_timing_derate -late -cell_delay 0.5 [get_cells "inst_1"]
puts "#### after 0.5 derate ####"
report_checks
write_timing_model -library_name base0p5_lib -cell base0p5 base0p5.lib

set_timing_derate -late -cell_delay 2.0 [get_cells "inst_1"]
puts "#### after 2.0 derate ####"
report_checks
write_timing_model -library_name base2p0_lib -cell base2p0 base2p0.lib

Relevant log output

base05p.lib and base2p0.lib don't reflect impact of set_timing_derate

Screenshots

No response

Additional Context

No response

[precisionmoon]

test.tar.gz
estimate.tcl reproduces the issue

[maliberty]

@tspyrou looks like one for Cherry

[rovinski]

I vaguely recall that this was actually intentional. It used to operate the way as described, but then the problem was that many users were misusing it. I think it may have been related to double-derating the timing when the block gets used at a higher level. Either way I'm sure Cherry will know.

[tspyrou]

I could ask Cherry to make it optional although I agree that normally the derating would be applied from the top.
@precisionmoon could you comment on the use case?

[precisionmoon]

One simple use model is to add an option to write_timing_model like -use_derate to honor STD. An info or warning message would be nice that explains that timing derates are being honored but this may lead to double-derating.

[tspyrou]

@precisionmoon lets discuss in our 1-1, I am skeptical that we should do this.

[maliberty]

@tspyrou is there a conclusion on this? close?