[Docs] Prototype for mermaid diagram by luarss · Pull Request #3559 · The-OpenROAD-Project/OpenROAD

luarss · 2023-06-30T17:09:38Z

Target is to have maintainable mermaid diagrams rather than svgs

Signed-off-by: luarss <espsluar@gmail.com>

vvbandeira · 2023-06-30T18:14:05Z

Thanks @luarss, this looks very promising.

FYI @maliberty, about your question regarding mermaid graphs. You can take a look at this first example, direct link here: https://openroad--3559.org.readthedocs.build/en/3559/main/README.html#getting-started-with-openroad-flow-scripts

maliberty · 2023-06-30T21:46:08Z

It looks very nice. If the font could be a bit bigger than would be good.

Signed-off-by: luarss <espsluar@gmail.com>

luarss · 2023-07-01T19:13:47Z

I fiddled around and it seems like mermaid boxes do not scale properly. If you try to increase the fontsize too much it will cover up the general step. Here's an example of 50px. The original is 16px.

maliberty · 2023-07-01T22:35:03Z

Is it possible to make the outer boxes flow top-to-bottom rather than left-to-right?

luarss · 2023-07-02T04:11:46Z

It will look something like this

Signed-off-by: luarss <espsluar@gmail.com>

luarss · 2023-07-07T06:04:12Z

Mockups for the figures in our main README

Design 1

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%

flowchart LR
    A[Verilog\n+ libraries\n + constraints] --> FLOW
    style A fill:#74c2b5
    subgraph FLOW
    style FLOW fill:#FFFFFF00,stroke-width:4px

    direction TB
        B[Logic Synthesis]
        B --> C[Floorplanning] 
        C --> D[Placement & Optimization]
        D --> E[CTS & Optimization]
        E --> F[Global & Detailed Routing]
        F --> G[Layout Finishing]
        style B fill:#f8cecc,stroke:#000000,stroke-width:4px
        style C fill:#fff2cc,stroke:#000000,stroke-width:4px
        style D fill:#cce5ff,stroke:#000000,stroke-width:4px
        style E fill:#67ab9f,stroke:#000000,stroke-width:4px
        style F fill:#fa6800,stroke:#000000,stroke-width:4px
        style G fill:#ff6666,stroke:#000000,stroke-width:4px
    end

    FLOW --> H[GDSII\n Final Layout]
    style H fill:#ff0000,stroke:#000000,stroke-width:4px

Design 2

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%

flowchart TB
    A[Verilog\n+ libraries\n + constraints] --> FLOW
    style A fill:#74c2b5
    subgraph FLOW
    style FLOW fill:#FFFFFF00,stroke-width:4px

    direction LR
        B[Logic Synthesis]
        B --> C[Floorplanning] 
        C --> D[Placement & Optimization]
        D --> E[CTS & Optimization]
        E --> F[Global & Detailed Routing]
        F --> G[Layout Finishing]
        style B fill:#f8cecc,stroke:#000000,stroke-width:4px
        style C fill:#fff2cc,stroke:#000000,stroke-width:4px
        style D fill:#cce5ff,stroke:#000000,stroke-width:4px
        style E fill:#67ab9f,stroke:#000000,stroke-width:4px
        style F fill:#fa6800,stroke:#000000,stroke-width:4px
        style G fill:#ff6666,stroke:#000000,stroke-width:4px
    end

    FLOW --> H[GDSII\n Final Layout]
    style H fill:#ff0000,stroke:#000000,stroke-width:4px

Design 3

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%

flowchart TB
    A[Verilog\n+ libraries\n + constraints] --> FLOW
    style A fill:#74c2b5
    subgraph FLOW
    style FLOW fill:#FFFFFF00,stroke-width:4px

    direction TB
        B[Logic Synthesis]
        B --> C[Floorplanning] 
        C --> D[Placement & Optimization]
        D --> E[CTS & Optimization]
        E --> F[Global & Detailed Routing]
        F --> G[Layout Finishing]
        style B fill:#f8cecc,stroke:#000000,stroke-width:4px
        style C fill:#fff2cc,stroke:#000000,stroke-width:4px
        style D fill:#cce5ff,stroke:#000000,stroke-width:4px
        style E fill:#67ab9f,stroke:#000000,stroke-width:4px
        style F fill:#fa6800,stroke:#000000,stroke-width:4px
        style G fill:#ff6666,stroke:#000000,stroke-width:4px
    end

    FLOW --> H[GDSII\n Final Layout]
    style H fill:#ff0000,stroke:#000000,stroke-width:4px

maliberty · 2023-07-07T06:10:17Z

I like design 3.

luarss · 2023-07-07T06:20:37Z

Mockups for the second figure link. Adding links are possible too.
Design 1 (split into 2 figures)

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%

flowchart LR
    A[RTL-GDSII\n Using\n OpenROAD-flow-scripts] --> 1:SYNTHESIS
    style A stroke:#000000,stroke-width:4px
    1:SYNTHESIS --> 2:FLOORPLAN; 
    subgraph 1:SYNTHESIS
    style 1:SYNTHESIS fill:#f8cecc,stroke:#000,stroke-width:4px
    direction LR
    B1(Tool:Yosys);  B2(Input files);  B3(Output files)
    B2 --> RTL & SDC & .lib & B4(Mapping files, etc..)
    B3 --> Netlist & B5(SDC)
    end
    subgraph 2:FLOORPLAN
    style 2:FLOORPLAN fill:#fff2cc,stroke:#000000,stroke-width:4px
    C1("Import all necessary files\n (Netlist, SDC, etc...) and
            check initial timing report")
    C1 --> C2("Translate .v to .odb/\n <a href='https://openroad.readthedocs.io/en/latest/main/src/ifp/README.html'>Floorplan Initialization</a>")
    C2 --> C3("IO placement (random)")
    C3 --> C4("Automatic partitioning")
    C4 --> C5("Timing-driven mixed-size placement")
    C5 --> C6("Macro placement/Hier-RTLMP")
    C6 --> C7("Tapcell and well tie insertion")
    C7 --> C8("PDN generation")
    C8 --> C9("Floorplan .odb and .sdc file generation")
    end

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%
flowchart LR
    3:PLACEMENT --> 4:CTS; 4:CTS --> 5:ROUTING; 5:ROUTING -->6:FINISH
    subgraph 3:PLACEMENT
    style 3:PLACEMENT fill:#cce5ff,stroke:#000000,stroke-width:4px
    D1("Global placement without placed IOs
                (Timing and routability-driven)")
    D1 --> D2("IO placement (non-random)")
    D2 --> D3("Global placement with placed IOs
                (Timing and routability-driven)")
    D3 --> D4("Resizing and buffering")
    D4 --> D5("Detailed placement")
    end
    subgraph 4:CTS
    style 4:CTS fill:#67ab9f,stroke:#000000,stroke-width:4px
    E1("Clock Tree synthesis")
    E1 --> E2("Timing optimization")
    E2 --> E3("Filler cell insertion")
    end
    subgraph 5:ROUTING
    style 5:ROUTING fill:#fa6800,stroke:#000000,stroke-width:4px
    F1("Global routing")
    F1 --> F2("Detailed routing")
    end
    subgraph 6:FINISH
    style 6:FINISH fill:#ff6666,stroke:#000000,stroke-width:4px
    G1("Generate GDSII Tool:\n KLayout")
    G1 --> G2("Metal Fill Insertion")
    G2 --> G3("Signoff timing report")
    G3 --> G4("DRC/LVS check\n Tool: Klayout")
    end

Design 2 (topdown)

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%

flowchart TB
    A[RTL-GDSII\n Using\n OpenROAD-flow-scripts] --> SYNTHESIS
    style A stroke:#000000,stroke-width:4px
    SYNTHESIS --> FLOORPLAN; 
    %% FLOORPLAN --> PLACEMENT; PLACEMENT --> CTS
    %%CTS --> ROUTING; ROUTING -->FINISH
    subgraph SYNTHESIS
    style SYNTHESIS fill:#f8cecc,stroke:#000,stroke-width:4px
    direction TB
    B1(Tool:Yosys);  B2(Input files);  B3(Output files)
    B2 --> RTL & SDC & .lib & B4(Mapping files, etc..)
    B3 --> Netlist & B5(SDC)
    end
    subgraph FLOORPLAN
    style FLOORPLAN fill:#fff2cc,stroke:#000000,stroke-width:4px
    C1("Import all necessary files\n (Netlist, SDC, etc...) and
            check initial timing report")
    C1 --> C2("Translate .v to .odb/\n Floorplan Initialization")
    C2 --> C3("IO placement (random)")
    C3 --> C4("Automatic partitioning")
    C4 --> C5("Timing-driven mixed-size placement")
    C5 --> C6("Macro placement/Hier-RTLMP")
    C6 --> C7("Tapcell and well tie insertion")
    C7 --> C8("PDN generation")
    C8 --> C9("Floorplan .odb and .sdc file generation")
    end

    FLOORPLAN--> PLACEMENT; PLACEMENT --> CTS; CTS --> ROUTING; ROUTING -->FINISH
    subgraph PLACEMENT
    style PLACEMENT fill:#cce5ff,stroke:#000000,stroke-width:4px
    D1("Global placement without placed IOs
                (Timing and routability-driven)")
    D1 --> D2("IO placement (non-random)")
    D2 --> D3("Global placement with placed IOs
                (Timing and routability-driven)")
    D3 --> D4("Resizing and buffering")
    D4 --> D5("Detailed placement")
    end
    subgraph CTS
    style CTS fill:#67ab9f,stroke:#000000,stroke-width:4px
    E1("Clock Tree synthesis")
    E1 --> E2("Timing optimization")
    E2 --> E3("Filler cell insertion")
    end
    subgraph ROUTING
    style ROUTING fill:#fa6800,stroke:#000000,stroke-width:4px
    F1("Global routing")
    F1 --> F2("Detailed routing")
    end
    subgraph FINISH
    style FINISH fill:#ff6666,stroke:#000000,stroke-width:4px
    G1("Generate GDSII Tool:\n KLayout")
    G1 --> G2("Metal Fill Insertion")
    G2 --> G3("Signoff timing report")
    G3 --> G4("DRC/LVS check\n Tool: Klayout")
    end

vvbandeira · 2023-07-07T13:11:32Z

I like design 3.

Me too.

For the second, maybe something like:

Detailed flow 1

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%
flowchart TB
    A[RTL-GDSII Using OpenROAD-flow-scripts] --> B --> C
    subgraph B[" "]
        style B stroke:#000000,stroke-width:4px
        1:SYNTHESIS --> 2:FLOORPLAN
        subgraph 1:SYNTHESIS
            style 1:SYNTHESIS fill:#f8cecc,stroke:#000,stroke-width:4px
            direction LR
            RTL & SDC & .lib & SYNTHESIS_2(Mapping files, etc..) --> SYNTHESIS_1(Yosys)
            SYNTHESIS_1 --> Netlist & SYNTHESIS_5(SDC)
        end
        subgraph 2:FLOORPLAN
          style 2:FLOORPLAN fill:#fff2cc,stroke:#000000,stroke-width:4px
          FLOORPLAN_1("Import all necessary files\n (Netlist, SDC, etc...) and
                  check initial timing report")
          FLOORPLAN_1 --> FLOORPLAN_2("Translate .v to .odb/\n <a href='https://openroad.readthedocs.io/en/latest/main/src/ifp/README.html'>Floorplan Initialization</a>")
          FLOORPLAN_2 --> FLOORPLAN_3("IO placement (random)")
          FLOORPLAN_3 --> FLOORPLAN_4("Automatic partitioning")
          FLOORPLAN_4 --> FLOORPLAN_5("Timing-driven mixed-size placement")
          FLOORPLAN_5 --> FLOORPLAN_6("Macro placement/Hier-RTLMP")
          FLOORPLAN_6 --> FLOORPLAN_7("Tapcell and well tie insertion")
          FLOORPLAN_7 --> FLOORPLAN_8("PDN generation")
          FLOORPLAN_8 --> FLOORPLAN_9(".odb") & .sdc
        end
    end
    subgraph C[" "]
        3:PLACEMENT --> C1; C1 --> 6:FINISH
        subgraph 3:PLACEMENT
            style 3:PLACEMENT fill:#cce5ff,stroke:#000000,stroke-width:4px
            PLACEMENT_1("Global placement without placed IOs
                        (Timing and routability-driven)")
            PLACEMENT_1 --> PLACEMENT_2("IO placement (non-random)")
            PLACEMENT_2 --> PLACEMENT_3("Global placement with placed IOs
                        (Timing and routability-driven)")
            PLACEMENT_3 --> PLACEMENT_4("Resizing and buffering")
            PLACEMENT_4 --> PLACEMENT_5("Detailed placement")
        end
        subgraph C1[" "]
            style C1 stroke-width:0px
            4:CTS --> 5:ROUTING
            subgraph 4:CTS
                direction TB
                CTS_1("Clock Tree synthesis")
                CTS_1 --> CTS_2("Timing optimization")
                CTS_2 --> CTS_3("Filler cell insertion")
            end
            subgraph 5:ROUTING
                style 5:ROUTING fill:#fa6800,stroke:#000000,stroke-width:4px
                ROUTING_1("Global routing")
                ROUTING_1 --> ROUTING_2("Detailed routing")
            end
        end
        subgraph 6:FINISH
            style 6:FINISH fill:#ff6666,stroke:#000000,stroke-width:4px
            FINISH_1("Generate GDSII Tool:\n KLayout")
            FINISH_1 --> FINISH_2("Metal Fill Insertion")
            FINISH_2 --> FINISH_3("Signoff timing report")
            FINISH_3 --> FINISH_4("DRC/LVS check\n Tool: Klayout")
        end
    end

Detailed flow 2

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%
flowchart TB
    BEGIN_NODE[RTL-GDSII Using OpenROAD-flow-scripts] --> FIRST_NODE --> SECOND_NODE
    subgraph FIRST_NODE[" "]
        style FIRST_NODE stroke:#000000,stroke-width:4px
        1:SYNTHESIS --> FIRST_A_1
        subgraph 1:SYNTHESIS
            style 1:SYNTHESIS fill:#f8cecc,stroke:#000,stroke-width:4px
            direction LR
            RTL & SDC & .lib & SYNTHESIS_2(Mapping files, etc..) --> SYNTHESIS_1(Yosys)
            SYNTHESIS_1 --> Netlist & SYNTHESIS_5(SDC)
        end
        subgraph FIRST_A_1["2:FLOORPLAN"]
            style FIRST_A_1 fill:#fff2cc,stroke:#000000,stroke-width:4px
            2:FLOORPLAN_A_1 --> 2:FLOORPLAN_A_2
            direction LR
            subgraph 2:FLOORPLAN_A_1[" "]
                style 2:FLOORPLAN_A_1 fill:#fff2cc,stroke:#000000,stroke-width:0px
                direction TB
                FLOORPLAN_1("Import all necessary files (Netlist, SDC, etc...)\n and check initial timing report")
                FLOORPLAN_1 --> FLOORPLAN_2("Translate .v to .odb/\n <a href='https://openroad.readthedocs.io/en/latest/main/src/ifp/README.html'>Floorplan Initialization</a>")
                FLOORPLAN_2 --> FLOORPLAN_3("IO placement (random)")
                FLOORPLAN_3 --> FLOORPLAN_4("Automatic partitioning")
                FLOORPLAN_4 --> FLOORPLAN_5("Timing-driven mixed-size placement")
            end
            subgraph 2:FLOORPLAN_A_2[" "]
                style 2:FLOORPLAN_A_2 fill:#fff2cc,stroke:#000000,stroke-width:0px
                direction TB
                FLOORPLAN_6("Macro placement/Hier-RTLMP")
                FLOORPLAN_6 --> FLOORPLAN_7("Tapcell and well tie insertion")
                FLOORPLAN_7 --> FLOORPLAN_8("PDN generation")
                FLOORPLAN_8 --> FLOORPLAN_9(".odb") & .sdc
            end
        end
    end
    subgraph SECOND_NODE[" "]
        3:PLACEMENT --> SECOND_A_1 --> 6:FINISH
        subgraph 3:PLACEMENT
            style 3:PLACEMENT fill:#cce5ff,stroke:#000000,stroke-width:4px
            PLACEMENT_1("Global placement without placed IOs
                                        (Timing and routability-driven)")
            PLACEMENT_1 --> PLACEMENT_2("IO placement (non-random)")
            PLACEMENT_2 --> PLACEMENT_3("Global placement with placed IOs 
                                                                          (Timing and routability-driven)")
            PLACEMENT_3 --> PLACEMENT_4("Resizing and buffering")
            PLACEMENT_4 --> PLACEMENT_5("Detailed placement")
        end
        subgraph SECOND_A_1[" "]
            style SECOND_A_1 stroke-width:0px
            4:CTS --> 5:ROUTING
            subgraph 4:CTS
                direction TB
                CTS_1("Clock Tree synthesis")
                CTS_1 --> CTS_2("Timing optimization")
                CTS_2 --> CTS_3("Filler cell insertion")
            end
            subgraph 5:ROUTING
                style 5:ROUTING fill:#fa6800,stroke:#000000,stroke-width:4px
                ROUTING_1("Global routing")
                ROUTING_1 --> ROUTING_2("Detailed routing")
            end
        end
        subgraph 6:FINISH
            style 6:FINISH fill:#ff6666,stroke:#000000,stroke-width:4px
            FINISH_1("Generate GDSII Tool:\n KLayout")
            FINISH_1 --> FINISH_2("Metal Fill Insertion")
            FINISH_2 --> FINISH_3("Signoff timing report")
            FINISH_3 --> FINISH_4("DRC/LVS check\n Tool: Klayout")
        end
    end

luarss · 2023-07-07T14:27:53Z

I think Detailed Flow 2 looks better. The input/outputs are clearer than before.

maliberty · 2023-07-07T14:34:06Z

In detailed #2 the sideways arrow in floorplan is confusing. It seems to imply some transformation rather than continuation.

luarss · 2023-07-07T17:24:02Z

@maliberty would it be better if we added numerical/alphabetical steps?

Detailed flow 2

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%
flowchart TB
    BEGIN_NODE[RTL-GDSII Using OpenROAD-flow-scripts] --> FIRST_NODE --> SECOND_NODE
    subgraph FIRST_NODE[" "]
        style FIRST_NODE stroke:#000000,stroke-width:4px
        1:SYNTHESIS --> FIRST_A_1
        subgraph 1:SYNTHESIS
            style 1:SYNTHESIS fill:#f8cecc,stroke:#000,stroke-width:4px
            direction LR
            RTL & SDC & .lib & SYNTHESIS_2(Mapping files, etc..) --> SYNTHESIS_1(Yosys)
            SYNTHESIS_1 --> Netlist & SYNTHESIS_5(SDC)
        end
        subgraph FIRST_A_1["2:FLOORPLAN"]
            style FIRST_A_1 fill:#fff2cc,stroke:#000000,stroke-width:4px
            2:FLOORPLAN_A_1 --- 2:FLOORPLAN_A_2
            direction LR
            subgraph 2:FLOORPLAN_A_1[" "]
                style 2:FLOORPLAN_A_1 fill:#fff2cc,stroke:#000000,stroke-width:0px
                direction TB
                FLOORPLAN_1("1) Import all necessary files (Netlist, SDC, etc...)\n and check initial timing report")
                FLOORPLAN_1 --> FLOORPLAN_2("2) Translate .v to .odb/\n <a href='https://openroad.readthedocs.io/en/latest/main/src/ifp/README.html'>Floorplan Initialization</a>")
                FLOORPLAN_2 --> FLOORPLAN_3("3) IO placement (random)")
                FLOORPLAN_3 --> FLOORPLAN_4("4) Automatic partitioning")
                FLOORPLAN_4 --> FLOORPLAN_5("5) Timing-driven mixed-size placement")
            end
            subgraph 2:FLOORPLAN_A_2[" "]
                style 2:FLOORPLAN_A_2 fill:#fff2cc,stroke:#000000,stroke-width:0px
                direction TB
                FLOORPLAN_6("6) Macro placement/Hier-RTLMP")
                FLOORPLAN_6 --> FLOORPLAN_7("7) Tapcell and well tie insertion")
                FLOORPLAN_7 --> FLOORPLAN_8("8) PDN generation")
                FLOORPLAN_8 --> FLOORPLAN_9(".odb") & .sdc
            end
        end
    end
    subgraph SECOND_NODE[" "]
        3:PLACEMENT --> SECOND_A_1 --> 6:FINISH
        subgraph 3:PLACEMENT
            style 3:PLACEMENT fill:#cce5ff,stroke:#000000,stroke-width:4px
            PLACEMENT_1("1) Global placement without placed IOs
                                        (Timing and routability-driven)")
            PLACEMENT_1 --> PLACEMENT_2("2) IO placement (non-random)")
            PLACEMENT_2 --> PLACEMENT_3("3) Global placement with placed IOs 
                                                                          (Timing and routability-driven)")
            PLACEMENT_3 --> PLACEMENT_4("4) Resizing and buffering")
            PLACEMENT_4 --> PLACEMENT_5("5) Detailed placement")
        end
        subgraph SECOND_A_1[" "]
            style SECOND_A_1 stroke-width:0px
            4:CTS --> 5:ROUTING
            subgraph 4:CTS
                direction TB
                CTS_1("1) CTS Tool: TritonCTS")
                CTS_1 --> CTS_2("2) Timing optimization")
                CTS_2 --> CTS_3("3) Filler cell insertion")
            end
            subgraph 5:ROUTING
                style 5:ROUTING fill:#fa6800,stroke:#000000,stroke-width:4px
                ROUTING_1("1) Global routing")
                ROUTING_1 --> ROUTING_2("2) Detailed routing")
            end
        end
        subgraph 6:FINISH
            style 6:FINISH fill:#ff6666,stroke:#000000,stroke-width:4px
            FINISH_1("1) Generate GDSII Tool:\n KLayout")
            FINISH_1 --> FINISH_2("2) Metal Fill Insertion")
            FINISH_2 --> FINISH_3("3) Signoff timing report")
            FINISH_3 --> FINISH_4("4) DRC/LVS check\n Tool: Klayout")
        end
    end

maliberty · 2023-07-07T20:02:46Z

It gets a bit confusing if the numbering doesn't match the numbering used in the steps of ORFS (eg CTS has three steps in the diagram but two in the flow). I find detailed flow 1 clearer but I'm curious what others think.

vijayank88 · 2023-07-08T06:11:47Z

@rovinski Please share your feedback for the flow diagram based on Mermaid.

rovinski · 2023-07-10T04:32:23Z

Honestly I'm not sure I like any of them. The viewer on GitHub isn't great because you can't click & drag to pan. The automatic resizing of text seems to make things too small quite often. It seems like there is quite a bit of hand-holding that needs to be done in order to get something that works as opposed to a WYSIWYG editor.

My two general points of feedback are that the text needs to be readable at it's default size and that my eyes should not have to guess where to look next. It should be a smooth, consistent flow diagram. Design 3 is the closest to that but adding in extra detail shouldn't make it harder to follow the substeps.

luarss · 2023-07-10T15:08:10Z

Full Flow Design 3

How about this? @rovinski @maliberty

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%

flowchart TB
    A[RTL-GDSII\n Using\n OpenROAD-flow-scripts] --> SYNTHESIS
    style A stroke:#000000,stroke-width:4px
    SYNTHESIS --> FLOORPLAN; 
    %% FLOORPLAN --> PLACEMENT; PLACEMENT --> CTS
    %%CTS --> ROUTING; ROUTING -->FINISH
    subgraph SYNTHESIS
    style SYNTHESIS fill:#f8cecc,stroke:#000,stroke-width:4px
    direction TB
    RTL & SDC & .lib & SYNTHESIS_2(Mapping files, etc..) --> SYNTHESIS_1(Yosys)
    SYNTHESIS_1 --> Netlist & SYNTHESIS_5(SDC)
    %%B1(Tool:Yosys);  B2(Input files);  B3(Output files)
    %%B2 --> RTL & SDC & .lib & B4(Mapping files, etc..)
    %%B3 --> Netlist & B5(SDC)
    end
    subgraph FLOORPLAN
    direction TB
    style FLOORPLAN fill:#fff2cc,stroke:#000000,stroke-width:4px
    C1("Import all necessary files\n (Netlist, SDC, etc...) and
            check initial timing report")
    C1 --> C2("Translate .v to .odb/\n Floorplan Initialization")
    C2 --> C3("IO placement (random)")
    C3 --> C4("Automatic partitioning")
    C4 --> C5("Timing-driven mixed-size placement")
    C5 --> C6("Macro placement/Hier-RTLMP")
    C6 --> C7("Tapcell and well tie insertion")
    C7 --> C8("PDN generation")
    C8 --> C9("Floorplan .odb and .sdc file generation")
    end

    FLOORPLAN--> PLACEMENT; PLACEMENT --> CTS; CTS --> ROUTING; ROUTING -->FINISH
    subgraph PLACEMENT
    direction TB
    style PLACEMENT fill:#cce5ff,stroke:#000000,stroke-width:4px
    D1("Global placement without placed IOs
                (Timing and routability-driven)")
    D1 --> D2("IO placement (non-random)")
    D2 --> D3("Global placement with placed IOs
                (Timing and routability-driven)")
    D3 --> D4("Resizing and buffering")
    D4 --> D5("Detailed placement")
    end
    subgraph CTS
    direction TB
    style CTS fill:#67ab9f,stroke:#000000,stroke-width:4px
    E1("Clock Tree synthesis")
    E1 --> E2("Timing optimization")
    E2 --> E3("Filler cell insertion")
    end
    subgraph ROUTING
    direction TB
    style ROUTING fill:#fa6800,stroke:#000000,stroke-width:4px
    F1("Global routing")
    F1 --> F2("Detailed routing")
    end
    subgraph FINISH
    direction TB
    style FINISH fill:#ff6666,stroke:#000000,stroke-width:4px
    G1("Generate GDSII Tool:\n KLayout")
    G1 --> G2("Metal Fill Insertion")
    G2 --> G3("Signoff timing report")
    G3 --> G4("DRC/LVS check\n Tool: Klayout")
    end

rovinski · 2023-07-10T18:14:52Z

Full Flow Design 3

How about this? @rovinski @maliberty

Cleaner, but now it doesn't fit on-screen. I have to scroll a lot to see the whole thing.

Signed-off-by: luarss <espsluar@gmail.com>

luarss · 2023-07-11T16:59:10Z

Check out this link for all the mermaid supported diagrams: https://mermaid.js.org/intro/
After exploring, I think our best hope is either flowchart or timeline, as attached in Design 4. Unfortunately, you cannot get rid of the bottom arrows.

Full Flow Design 4

timeline
    title RTL-GDSII Using OpenROAD-flow-scripts
    Synthesis: Inputs [RTL, SDC, .lib, .lef] 
            : Yosys
            : Output files [Netlist, SDC]
    Floorplan : Import all necessary files\n (Netlist, SDC, etc...)\n and check initial timing report
         : Translate .v to .odb/ \n Floorplan Initialization
         : IO placement (random)
         : Automatic partitioning
         : Timing-driven mixed-size placement
         : Macro placement/Hier-RTLMP
         : Tapcell and welltie insertion
         : PDN generation
         : Floorplan .odb and .sdc file generation
    Placement : Global placement without placed IOs\n (Timing and routability-driven)
        : IO placement (non-random)
        : Global placement with placed IOs \n (Timing and routability-driven)
        : Resizing and buffering
        : Detailed placement
    CTS : Clock Tree Synthesis
        : Timing optimization
        : Filler cell insertion

    Routing : Global Routing
            : Detailed Routing
    Finish  : Generate GDSII Tool: \n KLayout
            : Metal Fill insertion
            : Signoff timing report
            : DRC/LVS check\n Tool: KLayout

maliberty · 2023-07-11T18:23:17Z

I like it. One nit is \n in

vvbandeira · 2023-07-11T20:09:27Z

Looks like for this, \n should be <br>. I also removed the first two and last boxes in the floorplan -- I think they are not really needed.

timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs<br>[RTL, SDC, .lib, .lef]
    : Logic Synthesis<br>(Yosys)
    : Output files<br>[Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement<br>(random)
    : Automatic partitioning
    : Timing-driven mixed-size placement
    : Macro placement/Hier-RTLMP
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs<br>(Timing and routability-driven)
    : IO placement<br>(non-random)
    : Global placement with placed IOs<br>(Timing and routability-driven)
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finish
    : Generate GDSII<br>(KLayout)
    : Metal Fill insertion
    : Signoff timing report
    : DRC/LVS check<br>(KLayout)

maliberty · 2023-07-11T23:13:49Z

Some content notes:

What is "Automatic partitioning"?
"Macro placement/Hier-RTLMP" -> "Macro placement"
IO placement (non-random) -> IO placement (optimized)
Drop "(Timing and routability-driven)" in both gpl boxes. It's a detail that isn't needed at this level of detail.
"Generate GDSII" is after the final timing report
Finish -> Finishing

luarss · 2023-07-12T04:17:31Z

I believe automatic partitioning should be the step within MPL (RTL-MP) where they call ParquetFP.

timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs<br>[RTL, SDC, .lib, .lef]
    : Logic Synthesis<br>(Yosys)
    : Output files<br>[Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement<br>(random)
    : Automatic partitioning
    : Timing-driven mixed-size placement
    : Macro placement
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs<br>(Timing and routability-driven)
    : IO placement<br>(optimized)
    : Global placement with placed IOs
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finishing
    : Metal Fill insertion
    : Signoff timing report
    : Generate GDSII<br>(KLayout)
    : DRC/LVS check<br>(KLayout)

rovinski · 2023-07-12T05:36:07Z

This iteration is significantly better

maliberty · 2023-07-12T05:55:17Z

I believe automatic partitioning should be the step within MPL (RTL-MP) where they call ParquetFP.

MPL calls ParquetFP while RTL-MP does not. It is in both cases internal to macro placement and not a separate step.

vvbandeira · 2023-07-12T13:45:46Z

Removed the other "(Timing and routability-driven)" and dropped the "automatic partitioning".
If all agree, I think we can commit this version and move on with the PR.

timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs<br>[RTL, SDC, .lib, .lef]
    : Logic Synthesis<br>(Yosys)
    : Output files<br>[Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement<br>(random)
    : Timing-driven mixed-size placement
    : Macro placement
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs
    : IO placement<br>(optimized)
    : Global placement with placed IOs
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finishing
    : Metal Fill insertion
    : Signoff timing report
    : Generate GDSII<br>(KLayout)
    : DRC/LVS check<br>(KLayout)

vijayank88 · 2023-07-12T13:52:52Z

Unfortunately, you cannot get rid of the bottom arrows.

@vvbandeira didn't find any option to cut the rows?
Also updating each stage with unique color will be good.

vvbandeira · 2023-07-12T14:19:27Z

Unfortunately, you cannot get rid of the bottom arrows.

@vvbandeira didn't find any option to cut the rows? Also updating each stage with unique color will be good.

All the main stages have different colors already. Having different colors on the sub-steps, I think, will pollute too much.

luarss · 2023-07-12T14:55:26Z

Updated with the same colors as the high-level diagram.

%%{init: { 'logLevel': 'debug', 'titleColor' : '#808080', 
  'themeVariables': {
              'cScale0': '#f8cecc', 'cScaleLabel0': '#000',
              'cScale1': '#fff2cc', 'cScaleLabel1': '#000',
              'cScale2': '#cce5ff', 'cScaleLabel2': '#000',
              'cScale3': '#67ab9f', 'cScaleLabel3': '#000',
              'cScale4': '#fa6800', 'cScaleLabel4': '#000',
              'cScale5': '#ff6666', 'cScaleLabel5': '#000'
       } } }%%
timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs<br>[RTL, SDC, .lib, .lef]
    : Logic Synthesis<br>(Yosys)
    : Output files<br>[Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement<br>(random)
    : Timing-driven mixed-size placement
    : Macro placement
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs
    : IO placement<br>(optimized)
    : Global placement with placed IOs
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finishing
    : Metal Fill insertion
    : Signoff timing report
    : Generate GDSII<br>(KLayout)
    : DRC/LVS check<br>(KLayout)

maliberty · 2023-07-12T15:30:19Z

I like it except the colors of the substeps of the first steps don't seem to match.

luarss · 2023-07-12T15:35:33Z

I think its just a lighter shade. We can also choose from different themes

Dark

%%{init: { 'logLevel': 'debug', 'theme': 'dark'
  } }%%
timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs<br>[RTL, SDC, .lib, .lef]
    : Logic Synthesis<br>(Yosys)
    : Output files<br>[Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement<br>(random)
    : Timing-driven mixed-size placement
    : Macro placement
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs
    : IO placement<br>(optimized)
    : Global placement with placed IOs
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finishing
    : Metal Fill insertion
    : Signoff timing report
    : Generate GDSII<br>(KLayout)
    : DRC/LVS check<br>(KLayout)

Default

%%{init: { 'logLevel': 'debug', 'theme': 'default'
  } }%%
timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs<br>[RTL, SDC, .lib, .lef]
    : Logic Synthesis<br>(Yosys)
    : Output files<br>[Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement<br>(random)
    : Timing-driven mixed-size placement
    : Macro placement
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs
    : IO placement<br>(optimized)
    : Global placement with placed IOs
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finishing
    : Metal Fill insertion
    : Signoff timing report
    : Generate GDSII<br>(KLayout)
    : DRC/LVS check<br>(KLayout)

Forest

%%{init: { 'logLevel': 'debug', 'theme': 'forest'
  } }%%
timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs<br>[RTL, SDC, .lib, .lef]
    : Logic Synthesis<br>(Yosys)
    : Output files<br>[Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement<br>(random)
    : Timing-driven mixed-size placement
    : Macro placement
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs
    : IO placement<br>(optimized)
    : Global placement with placed IOs
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finishing
    : Metal Fill insertion
    : Signoff timing report
    : Generate GDSII<br>(KLayout)
    : DRC/LVS check<br>(KLayout)

Neutral

%%{init: { 'logLevel': 'debug', 'theme': 'neutral'
  } }%%
timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs<br>[RTL, SDC, .lib, .lef]
    : Logic Synthesis<br>(Yosys)
    : Output files<br>[Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement<br>(random)
    : Timing-driven mixed-size placement
    : Macro placement
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs
    : IO placement<br>(optimized)
    : Global placement with placed IOs
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finishing
    : Metal Fill insertion
    : Signoff timing report
    : Generate GDSII<br>(KLayout)
    : DRC/LVS check<br>(KLayout)

Base

%%{init: { 'logLevel': 'debug', 'theme': 'base'
  } }%%
timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs<br>[RTL, SDC, .lib, .lef]
    : Logic Synthesis<br>(Yosys)
    : Output files<br>[Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement<br>(random)
    : Timing-driven mixed-size placement
    : Macro placement
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs
    : IO placement<br>(optimized)
    : Global placement with placed IOs
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finishing
    : Metal Fill insertion
    : Signoff timing report
    : Generate GDSII<br>(KLayout)
    : DRC/LVS check<br>(KLayout)

maliberty · 2023-07-12T15:53:57Z

I don't love any but Dark seems the best to me

vvbandeira · 2023-07-12T16:23:03Z

%%{ init: {
    'logLevel': 'debug',
    'titleColor' : '#808080',
    'themeVariables':
      {
        'cScale0': '#94ec93', 'cScaleLabel0': '#000',
        'cScale1': '#4D904C', 'cScaleLabel1': '#000',
        'cScale2': '#75AE2E', 'cScaleLabel2': '#000',
        'cScale3': '#297ad6', 'cScaleLabel3': '#000',
        'cScale4': '#2060A9', 'cScaleLabel4': '#000',
        'cScale5': '#2749f1', 'cScaleLabel5': '#000'
      }
  }
}%%
timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs<br>[RTL, SDC, .lib, .lef]
    : Logic Synthesis<br>(Yosys)
    : Output files<br>[Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement<br>(random)
    : Timing-driven mixed-size placement
    : Macro placement
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs
    : IO placement<br>(optimized)
    : Global placement with placed IOs
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finishing
    : Metal Fill insertion
    : Signoff timing report
    : Generate GDSII<br>(KLayout)
    : DRC/LVS check<br>(KLayout)

3 blue / 3 green? Dark is also ok with me.

If anyone wants to play around and pick colors this and this might help.

maliberty · 2023-07-12T18:04:45Z

I find black text on blue to be hard to read.

luarss · 2023-07-13T16:45:53Z

I made some changes to the first flow and removed "Optimization" to be in line with detailed flow stages. I am thinking we can merge these first and then make aesthetic changes later on. Also mermaid supports UML diagrams but that can be a later PR.

Design 4

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%

flowchart TB
    A[Verilog\n+ libraries\n + constraints] --> FLOW
    style A fill:#74c2b5
    subgraph FLOW
    style FLOW fill:#FFFFFF00,stroke-width:4px

    direction TB
        B[Synthesis]
        B --> C[Floorplan] 
        C --> D[Placement]
        D --> E[Clock Tree Synthesis]
        E --> F[Routing]
        F --> G[Finishing]
        style B fill:#f8cecc,stroke:#000000,stroke-width:4px
        style C fill:#fff2cc,stroke:#000000,stroke-width:4px
        style D fill:#cce5ff,stroke:#000000,stroke-width:4px
        style E fill:#67ab9f,stroke:#000000,stroke-width:4px
        style F fill:#fa6800,stroke:#000000,stroke-width:4px
        style G fill:#ff6666,stroke:#000000,stroke-width:4px
    end

    FLOW --> H[GDSII\n Final Layout]
    style H fill:#ff0000,stroke:#000000,stroke-width:4px

Detailed Flow (dark)

%%{init: { 'logLevel': 'debug', 'theme': 'dark'
  } }%%
timeline
  title RTL-GDSII Using OpenROAD-flow-scripts
  Synthesis
    : Inputs<br>[RTL, SDC, .lib, .lef]
    : Logic Synthesis<br>(Yosys)
    : Output files<br>[Netlist, SDC]
  Floorplan
    : Floorplan Initialization
    : IO placement<br>(random)
    : Timing-driven mixed-size placement
    : Macro placement
    : Tapcell and welltie insertion
    : PDN generation
  Placement
    : Global placement without placed IOs
    : IO placement<br>(optimized)
    : Global placement with placed IOs
    : Resizing and buffering
    : Detailed placement
  CTS : Clock Tree Synthesis
    : Timing optimization
    : Filler cell insertion
  Routing
    : Global Routing
    : Detailed Routing
  Finishing
    : Metal Fill insertion
    : Signoff timing report
    : Generate GDSII<br>(KLayout)
    : DRC/LVS check<br>(KLayout)

maliberty · 2023-07-13T16:51:09Z

Its getting slow to load this PR due to all the diagram versions. Let's merge it and tweak as needed. @vvbandeira any further concerns?

vijayank88 · 2023-07-14T07:11:04Z

@luarss
I am unable to view Detailed Flow (dark) in your fork. Is that commit not pushed yet?
Syntheis and Floorplan looks same color almost. Just update different color.
Otherwise try to replicate same color used in Design 4 in ORFS flow too.

Signed-off-by: luarss <espsluar@gmail.com>

luarss · 2023-07-14T09:43:51Z

@vijayank88 Updated to latest.

vijayank88 · 2023-07-14T10:16:39Z

@vijayank88 Updated to latest.

Thanks @luarss . Can you please change dark color for first two stage to different color?
Then we will merge as per Matt's suggestion. Incremental PR change color based on user visibility.

luarss · 2023-07-14T13:11:18Z

@vijayank88 What other colors should we change to?

vijayank88 · 2023-07-14T13:30:07Z

@vijayank88 What other colors should we change to?

Let's Vitor to review and merge. In next PR, I will try to understand color format and change color. Thanks

prototype for mermaid diagram

cca68e3

Signed-off-by: luarss <espsluar@gmail.com>

vvbandeira self-requested a review June 30, 2023 18:12

made mermaid text bigger

1c1de3f

Signed-off-by: luarss <espsluar@gmail.com>

luarss added 2 commits July 2, 2023 15:33

font size 75px

bbe48c2

Signed-off-by: luarss <espsluar@gmail.com>

fix comment syntax mermaid

a3f264f

Signed-off-by: luarss <espsluar@gmail.com>

luarss marked this pull request as draft July 7, 2023 17:16

luarss added 2 commits July 11, 2023 03:06

add center align topdown

a33eee7

Signed-off-by: luarss <espsluar@gmail.com>

fix github readme revert links

e49b4aa

Signed-off-by: luarss <espsluar@gmail.com>

update latest mermaid

3d66bfc

Signed-off-by: luarss <espsluar@gmail.com>

luarss marked this pull request as ready for review July 14, 2023 09:44

vvbandeira approved these changes Jul 14, 2023

View reviewed changes

vvbandeira merged commit ba8f58d into The-OpenROAD-Project:master Jul 14, 2023

luarss deleted the mermaid_diagrams branch July 14, 2023 18:12

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Detailed flow 1

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