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1. 3-Stage-RV32IM-RISC-V-CPU 3-Stage-RV32IM-RISC-V-CPU Public

   tiny risc v implementation

   Verilog 3

2. PTGAN PTGAN Public

   Forked from ICCC-Platform/PTGAN

   2024_CV

   Python

3. Rare-Class-Enhancing-and-Prototype-Guided-Patch-Wise-Masking-for-Unsupervised-Domain-Adaptation Rare-Class-Enhancing-and-Prototype-Guided-Patch-Wise-Masking-for-Unsupervised-Domain-Adaptation Public

   Forked from Tsai-chia-hsiang/Rare-Class-Enhancing-and-Prototype-Guided-Patch-Wise-Masking-for-Unsupervised-Domain-Adaptation

   2024_CV_Implement of the Rare-Class Enhancing and Prototype-Guided Patch-Wise Masking for Unsupervised Domain Adaptation

   Python

4. All-Digital-Phase-Locked-Loop-ADPLL All-Digital-Phase-Locked-Loop-ADPLL Public

   All Digital Phase-Locked Loop (ADPLL)

   Verilog

5. IEEE-Standard-754-Floating-Point-Numbers-Multiplier IEEE-Standard-754-Floating-Point-Numbers-Multiplier Public

   This project implements a 64-bit IEEE 754 double-precision floating-point multiplier using Verilog HDL.

   Verilog