m5stack StackChan (based on CoreS3) doesn't boot/no CIRCUITPY drive

[wolfinabox]

CircuitPython version and board name

Adafruit CircuitPython 10.2.1; m5stack StackChan

Code/REPL

tio /dev/tty.usbmodem2101

Behavior

Build:Mar 27 2021
rst:0xc (RTC_SW_CPU_RST),boot:0x28 (SPI_FAST_FLASH_BOOT)
Saved PC:0x4038085e
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce2820,len:0x17f8
load:0x403c8700,len:0x4
load:0x403c8704,len:0xfa8
load:0x403cb700,len:0x30c0
entry 0x403c8974
I (26) boot: ESP-IDF v5.3.2 2nd stage bootloader
I (26) boot: compile time Jul  3 2025 10:56:32
I (26) boot: Multicore bootloader
I (29) boot: chip revision: v0.2
I (33) boot: efuse block revision: v1.3
I (38) qio_mode: Enabling default flash chip QIO
I (43) boot.esp32s3: Boot SPI Speed : 80MHz
I (48) boot.esp32s3: SPI Mode       : QIO
I (52) boot.esp32s3: SPI Flash Size : 16MB
I (57) boot: Enabling RNG early entropy source...
I (63) boot: Partition Table:
I (66) boot: ## Label            Usage          Type ST Offset   Length
I (74) boot:  0 nvs              WiFi data        01 02 00009000 00005000
I (81) boot:  1 otadata          OTA data         01 00 0000e000 00002000
I (88) boot:  2 ota_0            OTA app          00 10 00010000 00200000
I (96) boot:  3 ota_1            OTA app          00 11 00210000 00200000
I (103) boot:  4 uf2              factory app      00 00 00410000 00040000
I (111) boot:  5 ffat             Unknown data     01 81 00450000 00bb0000
I (119) boot: End of partition table
I (123) boot: Reset Reason = 12
I (127) boot: Reset hint = 0
I (130) esp_image: segment 0: paddr=00010020 vaddr=3c150020 size=4c57ch (312700) map
I (185) esp_image: segment 1: paddr=0005c5a4 vaddr=3fca0800 size=03a74h ( 14964) load
I (188) esp_image: segment 2: paddr=00060020 vaddr=42000020 size=14721ch (1339932) map
I (391) esp_image: segment 3: paddr=001a7244 vaddr=3fca4274 size=015f4h (  5620) load
I (393) esp_image: segment 4: paddr=001a8840 vaddr=40374000 size=1c6f4h (116468) load
I (419) esp_image: segment 5: paddr=001c4f3c vaddr=50001fd0 size=00020h (    32) load
I (419) esp_image: segment 6: paddr=001c4f64 vaddr=600fe000 size=01060h (  4192) load
I (437) boot: Loaded app from partition at offset 0x10000
I (437) boot: Disabling RNG early entropy source...

Description

The m5stack StackChan is based on the m5stack CoreS3, with an added servo base with some peripherals.
I'm attempting to flash CircuitPython for the CoreS3 on it.

After using the "Open installer" workflow from the CircuitPython page, no CIRCUITPY drive ever appears, and the boot log over USB serial ends at I (437) boot: Disabling RNG early entropy source... (full log in "Behavior").
The backlight remains on while the unit is plugged in.
I've tried removing the CoreS3 unit from the StackChan base and flashing that way, same result.
Same result flashing the bootloader with esptool as well.

Additional information

Flashing on an M1 Max MBP on Tahoe 26.3.1

[dhalbert]

Could you try 10.3.0-alpha.2? Thanks.

[dhalbert]

Also try

https://circuitpython.org/board/yd_esp32_s3_n16r8/
and

https://circuitpython.org/board/adafruit_metro_esp32s3/

These are more generic 16/8 boards

[wolfinabox]

@dhalbert Same result with CoreS3 10.3.0-alpha.2. After the .uf2 gets copied to the CORES3BOOT drive, the board doesn't seem to reset. I press the reset button, and get this boot log after attaching to the serial monitor:

CoreS3 10.3.0-alpha.2 boot log

ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0xc (RTC_SW_CPU_RST),boot:0x2b (SPI_FAST_FLASH_BOOT)
Saved PC:0x4038316e
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce2820,len:0x17f8
load:0x403c8700,len:0x4
load:0x403c8704,len:0xfa8
load:0x403cb700,len:0x30c0
entry 0x403c8974
I (26) boot: ESP-IDF v5.3.2 2nd stage bootloader
I (26) boot: compile time Jul  3 2025 10:56:32
I (26) boot: Multicore bootloader
I (29) boot: chip revision: v0.2
I (33) boot: efuse block revision: v1.3
I (38) qio_mode: Enabling default flash chip QIO
I (43) boot.esp32s3: Boot SPI Speed : 80MHz
I (48) boot.esp32s3: SPI Mode       : QIO
I (52) boot.esp32s3: SPI Flash Size : 16MB
I (57) boot: Enabling RNG early entropy source...
I (63) boot: Partition Table:
I (66) boot: ## Label            Usage          Type ST Offset   Length
I (74) boot:  0 nvs              WiFi data        01 02 00009000 00005000
I (81) boot:  1 otadata          OTA data         01 00 0000e000 00002000
I (88) boot:  2 ota_0            OTA app          00 10 00010000 00200000
I (96) boot:  3 ota_1            OTA app          00 11 00210000 00200000
I (103) boot:  4 uf2              factory app      00 00 00410000 00040000
I (111) boot:  5 ffat             Unknown data     01 81 00450000 00bb0000
I (119) boot: End of partition table
I (123) boot: Reset Reason = 12
I (127) boot: Reset hint = 0
I (130) esp_image: segment 0: paddr=00010020 vaddr=3c160020 size=4ea20h (322080) map
I (187) esp_image: segment 1: paddr=0005ea48 vaddr=3fc9e900 size=015d0h (  5584) load
I (188) esp_image: segment 2: paddr=00060020 vaddr=42000020 size=156d64h (1404260) map
I (402) esp_image: segment 3: paddr=001b6d8c vaddr=3fc9fed0 size=04bech ( 19436) load
I (406) esp_image: segment 4: paddr=001bb980 vaddr=40374000 size=1a8b4h (108724) load
I (428) esp_image: segment 5: paddr=001d623c vaddr=50001fd0 size=00024h (    36) load
I (429) esp_image: segment 6: paddr=001d6268 vaddr=600fe000 size=00060h (    96) load
I (445) boot: Loaded app from partition at offset 0x10000
I (445) boot: Disabling RNG early entropy source...

YD-ESP32-S3 10.3.0-alpha.2 seems to have a similar output, but boot loops constantly (with this same output) instead of just stopping.

YD-ESP32-S3 10.3.0-alpha.2

ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0xc (RTC_SW_CPU_RST),boot:0x28 (SPI_FAST_FLASH_BOOT)
Saved PC:0x40386082
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce2810,len:0x1670
load:0x403c8700,len:0x4
load:0x403c8704,len:0xf84
load:0x403cb700,len:0x2e34
entry 0x403c8a24
I (26) boot: ESP-IDF v5.3.2 2nd stage bootloader
I (26) boot: compile time Jul  3 2025 10:58:56
I (26) boot: Multicore bootloader
I (29) boot: chip revision: v0.2
I (33) boot: efuse block revision: v1.3
I (38) boot.esp32s3: Boot SPI Speed : 80MHz
I (42) boot.esp32s3: SPI Mode       : DIO
I (47) boot.esp32s3: SPI Flash Size : 16MB
I (52) boot: Enabling RNG early entropy source...
I (57) boot: Partition Table:
I (61) boot: ## Label            Usage          Type ST Offset   Length
I (68) boot:  0 nvs              WiFi data        01 02 00009000 00005000
I (76) boot:  1 otadata          OTA data         01 00 0000e000 00002000
I (83) boot:  2 ota_0            OTA app          00 10 00010000 00200000
I (91) boot:  3 ota_1            OTA app          00 11 00210000 00200000
I (98) boot:  4 uf2              factory app      00 00 00410000 00040000
I (106) boot:  5 ffat             Unknown data     01 81 00450000 00bb0000
I (113) boot: End of partition table
I (117) boot: Reset Reason = 12
I (121) boot: Reset hint = 4
I (125) esp_image: segment 0: paddr=00010020 vaddr=3c170020 size=49044h (299076) map
I (186) esp_image: segment 1: paddr=0005906c vaddr=3fc9f200 size=0617ch ( 24956) load
I (191) esp_image: segment 2: paddr=0005f1f0 vaddr=40374000 size=00e28h (  3624) load
I (193) esp_image: segment 3: paddr=00060020 vaddr=42000020 size=169d9ch (1482140) map
I (461) esp_image: segment 4: paddr=001c9dc4 vaddr=40374e28 size=1a308h (107272) load
I (485) esp_image: segment 5: paddr=001e40d4 vaddr=50001fd0 size=00024h (    36) load
I (486) esp_image: segment 6: paddr=001e4100 vaddr=600fe000 size=00060h (    96) load
I (502) boot: Loaded app from partition at offset 0x10000
I (502) boot: Disabling RNG early entropy source...
(boot loops here)

And a similar result for the Metro ESP32-S3 0.3.0-alpha.2, boot looping as well

Metro ESP32-S3 0.3.0-alpha.2

ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0xc (RTC_SW_CPU_RST),boot:0x2a (SPI_FAST_FLASH_BOOT)
Saved PC:0x40386082
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce2820,len:0x1854
load:0x403c8700,len:0x4
load:0x403c8704,len:0x120c
load:0x403cb700,len:0x30c0
entry 0x403c8a5c
I (26) boot: ESP-IDF v5.3.2 2nd stage bootloader
I (26) boot: compile time Jul  3 2025 10:50:40
I (26) boot: Multicore bootloader
I (29) boot: chip revision: v0.2
I (33) boot: efuse block revision: v1.3
I (38) qio_mode: Enabling default flash chip QIO
I (43) boot.esp32s3: Boot SPI Speed : 80MHz
I (48) boot.esp32s3: SPI Mode       : QIO
I (52) boot.esp32s3: SPI Flash Size : 16MB
I (57) boot: Enabling RNG early entropy source...
I (63) boot: Partition Table:
I (66) boot: ## Label            Usage          Type ST Offset   Length
I (74) boot:  0 nvs              WiFi data        01 02 00009000 00005000
I (81) boot:  1 otadata          OTA data         01 00 0000e000 00002000
I (89) boot:  2 ota_0            OTA app          00 10 00010000 00200000
I (96) boot:  3 ota_1            OTA app          00 11 00210000 00200000
I (103) boot:  4 uf2              factory app      00 00 00410000 00040000
I (111) boot:  5 ffat             Unknown data     01 81 00450000 00bb0000
I (119) boot: End of partition table
I (123) boot: Reset Reason = 12
I (127) boot: Reset hint = 4
I (130) esp_image: segment 0: paddr=00010020 vaddr=3c170020 size=48dd4h (298452) map
I (183) esp_image: segment 1: paddr=00058dfc vaddr=3fc9f200 size=0617ch ( 24956) load
I (188) esp_image: segment 2: paddr=0005ef80 vaddr=40374000 size=01098h (  4248) load
I (190) esp_image: segment 3: paddr=00060020 vaddr=42000020 size=169ddch (1482204) map
I (417) esp_image: segment 4: paddr=001c9e04 vaddr=40375098 size=1a098h (106648) load
I (438) esp_image: segment 5: paddr=001e3ea4 vaddr=50001fd0 size=00024h (    36) load
I (438) esp_image: segment 6: paddr=001e3ed0 vaddr=600fe000 size=00060h (    96) load
I (455) boot: Loaded app from partition at offset 0x10000
I (455) boot: Disabling RNG early entropy source...
(boot loops here)

[dhalbert]

I see that the schematic for the CoreS3 baseboard is the same for both products.

Did you erase flash completely in the process of the loading the firmware?

You could try loading the .bin after a full erase, instead of using the .uf2 + the bootloader.

Do you have any other Espressif S3 boards that you could try, just to rule out an issue with the flashing process?

This board definition was contributed by @CDarius. We don't have one of these boards to test (I have a Cardputer, which is a Stamp S3A. I just tried 10.2.1 and it is fine.) @CDarius, have you seen this with recent builds your CoreS3 (if you have one)?

[wolfinabox]

@dhalbert
I didn't click "Skip Erase", so yes it should have. I've also tried erasing the flash with esptool (pipx run esptool --port /dev/tty.usbmodem2101 erase-flash) beforehand.
I get the same result flashing the .bin directly as well.

Unfortunately I don't have another supported S3 board to test on atm; flashing a Pico 2W via dragging .uf2 worked fine though (though that's not exactly the same method), and flashing the stock/test firmware from m5stack works fine. I've also had no issue flashing it with esphome via their web flasher

[CDarius]

I made a quick test and the last working version of CircuitPython on CoreS3 seams to be 10.0.3. Starting from 10.1.1 doesn't boot anymore.

[dhalbert]

@tannewt do you happen to have a CoreS3? If not maybe one of us should get one.

[tannewt]

@tannewt do you happen to have a CoreS3? If not maybe one of us should get one.

I don't believe I do. I'd rather leave this as community supported (aka we don't get one) because I'd like some pressure on m5stack to support their boards in CP. Maybe they'll be more open to it now that they are owned by Espressif.

Otherwise, I'd encourage folks to find other boards with the same issue. We can look into it if they are Adafruit boards.

[dhalbert]

I tried the S3 Box build with recent builds, because it is vaguely similar, but it was fine.

Could you put a CoreS3 into ROM bootloader mode, run the esptool chip-id and flash-id commands, and post the output? This might reveal something different about these boards.

EDIT: see newer suggestions in next post.

Also see if any of these builds work. Use the .bin versions and erase flash beforehand to avoid any possible effect by a UF2 bootloader.
https://circuitpython.org/board/espressif_esp32s3_devkitc_1_n8/ (8MB flash / no PSRAM)
https://circuitpython.org/board/espressif_esp32s3_devkitc_1_n16/ (16/0)
https://circuitpython.org/board/espressif_esp32s3_devkitc_1_n8r8/ (8/8)
https://circuitpython.org/board/espressif_esp32s3_devkitc_1_n8r2/ (8/2)
https://circuitpython.org/board/espressif_esp32s3_devkitm_1_n8/ (8/0)

[dhalbert]

An LLM query suggests this might be a PSRAM mode issue (OPI vs QIO). Why this problem appeared when CircuitPython upgrade to v5.5.3 is unclear to me.

LLM suggestions, which make sense to me.

Good QIO-PSRAM builds to try:

1. circuitart_zero_s3 — closest match I found: ESP32-S3, 16MB flash, 8MB QIO PSRAM
2. espressif_esp32s3_devkitc_1_n8r2 — ESP32-S3, 8MB flash, 2MB QIO PSRAM
3. unexpectedmaker_tinywatch_s3 or bpi_picow_s3 — also ESP32-S3 with QIO PSRAM, though only 2MB PSRAM

The LLM also noted that the CoreS3 boards reuse the strapping pins in unusual ways and have custom reset and ROM bootloader entry circuitry.

[wolfinabox]

@dhalbert

esptool chip-id

esptool v5.2.0
Connected to ESP32-S3 on /dev/cu.usbmodem2101:
Chip type:          ESP32-S3 (QFN56) (revision v0.2)
Features:           Wi-Fi, BT 5 (LE), Dual Core + LP Core, 240MHz
Crystal frequency:  40MHz
USB mode:           USB-Serial/JTAG
MAC:                44:1b:f6:e2:9a:8c

Stub flasher running.

Warning: ESP32-S3 has no chip ID. Reading MAC address instead.
MAC:                44:1b:f6:e2:9a:8c

Hard resetting via RTS pin...

esptool flash-id

esptool v5.2.0
Connected to ESP32-S3 on /dev/cu.usbmodem2101:
Chip type:          ESP32-S3 (QFN56) (revision v0.2)
Features:           Wi-Fi, BT 5 (LE), Dual Core + LP Core, 240MHz
Crystal frequency:  40MHz
USB mode:           USB-Serial/JTAG
MAC:                44:1b:f6:e2:9a:8c

Stub flasher running.

Flash Memory Information:
=========================
Manufacturer: 46
Device: 4018
Detected flash size: 16MB
Flash type set in eFuse: quad (4 data lines)
Flash voltage set by a strapping pin: 3.3V

Hard resetting via RTS pin...

ESP32-S3-DevKitC-1-N8: Works

ESP32-S3-DevKitC-1-N16: Works

ESP32-S3-DevKitC-1-N8R8: **Boot-loops (logs)**

ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0xc (RTC_SW_CPU_RST),boot:0x28 (SPI_FAST_FLASH_BOOT)
Saved PC:0x403837e9
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce2820,len:0x17fc
load:0x403c8700,len:0x4
load:0x403c8704,len:0x1120
load:0x403cb700,len:0x30c0
entry 0x403c8a4c
I (26) boot: ESP-IDF v5.3.2 2nd stage bootloader
I (26) boot: compile time Jul  3 2025 10:50:56
I (26) boot: Multicore bootloader
I (29) boot: chip revision: v0.2
I (33) boot: efuse block revision: v1.3
I (38) qio_mode: Enabling default flash chip QIO
I (43) boot.esp32s3: Boot SPI Speed : 80MHz
I (48) boot.esp32s3: SPI Mode       : QIO
I (52) boot.esp32s3: SPI Flash Size : 8MB
I (57) boot: Enabling RNG early entropy source...
I (63) boot: Partition Table:
I (66) boot: ## Label            Usage          Type ST Offset   Length
I (73) boot:  0 nvs              WiFi data        01 02 00009000 00005000
I (81) boot:  1 otadata          OTA data         01 00 0000e000 00002000
I (88) boot:  2 ota_0            OTA app          00 10 00010000 00200000
I (96) boot:  3 ota_1            OTA app          00 11 00210000 00200000
I (103) boot:  4 uf2              factory app      00 00 00410000 00040000
I (111) boot:  5 ffat             Unknown data     01 81 00450000 003b0000
I (119) boot: End of partition table
I (123) boot: Reset Reason = 12
I (127) boot: Reset hint = 4
I (130) esp_image: segment 0: paddr=00010020 vaddr=3c160020 size=46770h (288624) map
I (181) esp_image: segment 1: paddr=00056798 vaddr=3fca1000 size=05028h ( 20520) load
I (185) esp_image: segment 2: paddr=0005b7c8 vaddr=40374000 size=04850h ( 18512) load
I (191) esp_image: segment 3: paddr=00060020 vaddr=42000020 size=1598b8h (1415352) map
I (406) esp_image: segment 4: paddr=001b98e0 vaddr=40378850 size=18744h (100164) load
I (425) esp_image: segment 5: paddr=001d202c vaddr=50001fd0 size=00020h (    32) load
I (426) esp_image: segment 6: paddr=001d2054 vaddr=600fe000 size=01060h (  4192) load
I (444) boot: Loaded app from partition at offset 0x10000
I (444) boot: Disabling RNG early entropy source...

ESP32-S3-DevKitC-1-N8R2: Works

ESP32-S3-DevKitM-1-N8: Works

All done with the "Open installer" workflow, CircuitPython 10.3.0-alpha.2