Pinned Loading

1. AXI_PWM_DAC AXI_PWM_DAC Public

   DAC with PWM output for ZYNQ or FPGA, S_AXIS Data input and one Pin PWM data output

   Tcl 1 2

2. S9-defination S9-defination Public

   Antminer S9 Board defination file for VIVADO

   4 2

3. Wave_Reader Wave_Reader Public

   Wave file reader with buffer for AXI DMA in ZYNQ PS bare-metal

   C 3

4. zynq-axi-dna zynq-axi-dna Public

   Forked from nengo/zynq-axi-dna

   IP core with AXI interface for reading the Device DNA from the PL of Zynq 7000 devices

   Tcl 1 1

5. zynq_wave_player zynq_wave_player Public

   VIVADO Project for ZYNQ 7010 S9 wave player

   Python 2 2