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Merged
xiaoxiang781216 merged 3 commits into from
Feb 21, 2023
Merged

i.mxrt d-cache write-back mode with networking #8603

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b612a49
arch: imxrt: Fix CONFIG_IMXRT_ENET_ENHANCEDBD
masayuki2009 Feb 20, 2023
9492250
arch: imxrt: Enable IMXRT_ENET_ENHANCEDBD if !ARMV7M_DCACHE_WRITETHROUGH
masayuki2009 Feb 20, 2023
fa6d489
boards: imxrt1060-evk: Add netnsh_dcache_wb configuration
masayuki2009 Feb 20, 2023
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3 changes: 2 additions & 1 deletion arch/arm/src/imxrt/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -2070,7 +2070,8 @@ config IMXRT_ENET_NTXBUFFERS

config IMXRT_ENET_ENHANCEDBD
bool # not optional
default n
default n if ARMV7M_DCACHE_WRITETHROUGH
default y if !ARMV7M_DCACHE_WRITETHROUGH

config IMXRT_ENET_NETHIFS
int # Not optional
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6 changes: 3 additions & 3 deletions arch/arm/src/imxrt/hardware/imxrt_enet.h
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Expand Up @@ -640,7 +640,7 @@

/* Legacy Buffer Descriptor */

#ifdef CONFIG_ENET_ENHANCEDBD
#ifdef CONFIG_IMXRT_ENET_ENHANCEDBD
#ifdef IMXRT_USE_DBSWAP
/* When DBSWP is used to swap the bytes in hardware, it is done 32-bits
* at a time. Therefore, all 16 bit elements need to be swapped to
Expand Down Expand Up @@ -675,7 +675,7 @@ struct enet_desc_s
uint32_t reserved2; /* unused */
};
#endif /* IMXRT_USE_DBSWAP */
#else /* CONFIG_ENET_ENHANCEDBD */
#else /* CONFIG_IMXRT_ENET_ENHANCEDBD */
#ifdef IMXRT_USE_DBSWAP
struct enet_desc_s
{
Expand All @@ -691,7 +691,7 @@ struct enet_desc_s
uint8_t *data; /* Buffer address */
};
#endif /* IMXRT_USE_DBSWAP */
#endif /* CONFIG_ENET_ENHANCEDBD */
#endif /* CONFIG_IMXRT_ENET_ENHANCEDBD */

/****************************************************************************
* Public Data
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11 changes: 6 additions & 5 deletions arch/arm/src/imxrt/imxrt_enet.c
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Expand Up @@ -159,7 +159,8 @@
* REVISIT: The size of descriptors and buffers must also be in even units
* of the cache line size That is because the operations to clean and
* invalidate the cache will operate on a full 32-byte cache line. If
* CONFIG_ENET_ENHANCEDBD is selected, then the size of the descriptor is
* CONFIG_IMXRT_ENET_ENHANCEDBD is selected,
* then the size of the descriptor is
* 32-bytes (and probably already the correct size for the cache line);
* otherwise, the size of the descriptors much smaller, only 8 bytes.
*/
Expand Down Expand Up @@ -665,7 +666,7 @@ static int imxrt_transmit(struct imxrt_driver_s *priv)
*/

txdesc->length = imxrt_swap16(priv->dev.d_len);
#ifdef CONFIG_IMXRT_ENETENHANCEDBD
#ifdef CONFIG_IMXRT_ENET_ENHANCEDBD
txdesc->bdu = 0x00000000;
txdesc->status2 = TXDESC_INT | TXDESC_TS; /* | TXDESC_IINS | TXDESC_PINS; */
#endif
Expand Down Expand Up @@ -1343,7 +1344,7 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy)

/* Select legacy of enhanced buffer descriptor format */

#ifdef CONFIG_IMXRT_ENETENHANCEDBD
#ifdef CONFIG_IMXRT_ENET_ENHANCEDBD
imxrt_enet_putreg32(priv, ENET_ECR_EN1588, IMXRT_ENET_ECR_OFFSET);
#else
imxrt_enet_putreg32(priv, 0, IMXRT_ENET_ECR_OFFSET);
Expand Down Expand Up @@ -2608,7 +2609,7 @@ static void imxrt_initbuffers(struct imxrt_driver_s *priv)
priv->txdesc[i].status1 = 0;
priv->txdesc[i].length = 0;
priv->txdesc[i].data = (uint8_t *)imxrt_swap32((uint32_t)addr);
#ifdef CONFIG_IMXRT_ENETENHANCEDBD
#ifdef CONFIG_IMXRT_ENET_ENHANCEDBD
priv->txdesc[i].status2 = TXDESC_IINS | TXDESC_PINS;
#endif
addr += ALIGNED_BUFSIZE;
Expand All @@ -2621,7 +2622,7 @@ static void imxrt_initbuffers(struct imxrt_driver_s *priv)
priv->rxdesc[i].status1 = RXDESC_E;
priv->rxdesc[i].length = 0;
priv->rxdesc[i].data = (uint8_t *)imxrt_swap32((uint32_t)addr);
#ifdef CONFIG_IMXRT_ENETENHANCEDBD
#ifdef CONFIG_IMXRT_ENET_ENHANCEDBD
priv->rxdesc[i].bdu = 0;
priv->rxdesc[i].status2 = RXDESC_INT;
#endif
Expand Down
86 changes: 86 additions & 0 deletions boards/arm/imxrt/imxrt1060-evk/configs/netnsh_dcache_wb/defconfig
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@@ -0,0 +1,86 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_ARCH_LEDS is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="imxrt1060-evk"
CONFIG_ARCH_BOARD_IMXRT1060_EVK=y
CONFIG_ARCH_CHIP="imxrt"
CONFIG_ARCH_CHIP_IMXRT=y
CONFIG_ARCH_CHIP_MIMXRT1062DVL6A=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARMV7M_DCACHE=y
CONFIG_ARMV7M_ICACHE=y
CONFIG_ARMV7M_USEBASEPRI=y
CONFIG_BOARD_LOOPSPERMSEC=104926
CONFIG_BUILTIN=y
CONFIG_DEBUG_BUSFAULT=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_HARDFAULT_ALERT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEBUG_USAGEFAULT=y
CONFIG_ETH0_PHY_KSZ8081=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_IMXRT_ENET=y
CONFIG_IMXRT_ENET_NRXBUFFERS=64
CONFIG_IMXRT_ENET_NTXBUFFERS=64
CONFIG_IMXRT_LPUART1=y
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INIT_STACKSIZE=3072
CONFIG_INTELHEX_BINARY=y
CONFIG_IOB_BUFSIZE=1514
CONFIG_LIBC_HOSTNAME="i.MXRT1060 EVK"
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_NET=y
CONFIG_NETDB_DNSCLIENT=y
CONFIG_NETDEV_STATISTICS=y
CONFIG_NETINIT_NOMAC=y
CONFIG_NETUTILS_IPERF=y
CONFIG_NETUTILS_TELNETD=y
CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ETH_PKTSIZE=1514
CONFIG_NET_GUARDSIZE=4
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_ICMPv6=y
CONFIG_NET_ICMPv6_NEIGHBOR=y
CONFIG_NET_ICMPv6_SOCKET=y
CONFIG_NET_IPv6=y
CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_UDP=y
CONFIG_NET_UDP_WRITE_BUFFERS=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_RAM_SIZE=1048576
CONFIG_RAM_START=0x20200000
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_START_DAY=20
CONFIG_START_MONTH=2
CONFIG_START_YEAR=2023
CONFIG_SYSLOG_TIMESTAMP=y
CONFIG_SYSTEM_DHCPC_RENEW=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_PING6=y
CONFIG_SYSTEM_PING=y
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_TESTING_OSTEST_NBARRIER_THREADS=3
CONFIG_TESTING_OSTEST_STACKSIZE=2048